In-Memory Vector Neural Network for Complex MAC Efficiency
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Solution Overview
Problem
Existing neural network architectures, particularly those using von Neumann architectures, face inefficiencies in data transmission and power consumption due to separate operation units and memory, and fail to effectively utilize the correlation between real and imaginary elements in complex and quaternion-based neural networks, leading to reduced training and inference performance.
Innovation Solution
A multidimensional vector neural network architecture that integrates memory and operation units, utilizing a crossbar array with selectors and adders to perform complex and quaternion-based MAC operations efficiently, maintaining the correlation between real and imaginary elements by storing weight elements in reference memory cells connected to different output lines and employing selectors to transmit values with appropriate signs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional digital computer architecture with separate operation units and memory is used, then neural network operations can be performed, but computational complexity and power consumption increase
Solution Approach 1:
The patent merges memory cells and operation units (selectors and adders) into an integrated in-memory computing architecture. Memory cells store weight elements while being directly connected to selectors and adders, enabling MAC operations to be performed within the memory array itself rather than requiring separate computation units. This integration eliminates data transfer between memory and processing units, reducing both power consumption and computational complexity.
Solution Approach 2:
The patent introduces crossbar array architecture as an intermediary structure between memory and computation. The crossbar array with its switching elements (selectors) acts as a mediator that enables direct interaction between stored weight elements and input data, facilitating efficient MAC operations without requiring traditional separate processing units. This intermediary structure is key to achieving in-memory computing benefits.
2Productivity
If in-memory computing with crossbar array architecture is implemented, then MAC operations are performed efficiently, but device structure becomes more complex
Solution Approach 1:
The patent designs the crossbar array architecture to perform multiple functions: memory cells store weight elements, selectors route data between input lines and adders, and adders accumulate results. This multi-functional integration within the memory array structure enables efficient MAC operations while avoiding the need for separate dedicated computation units, thereby improving productivity without proportionally increasing overall device complexity.
Solution Approach 2:
The patent transitions from traditional sequential computation to a parallel in-memory computing paradigm by organizing computation operations across the two-dimensional crossbar array structure. Multiple MAC operations are performed simultaneously across different memory cells and adders in parallel, dramatically improving operation efficiency. The spatial dimensionality of the crossbar array enables this parallelism without requiring proportional increases in control complexity.
3Adaptability or versatility
If weight elements are stored in reference memory cells connecting single reference input line and multiple reference output lines, then multidimensional vector operations are enabled, but memory cell connectivity requirements increase
Solution Approach 1:
The patent implements dynamic connectivity control through selectors that can route signals between reference input lines and reference output lines based on operational requirements. The selectors enable the memory array to adaptively reconfigure its connectivity pattern, allowing single reference input lines to connect to multiple reference output lines when needed for multidimensional vector operations. This dynamic routing capability provides versatility without requiring permanent complex interconnections between all memory cells.
Data Source
AI summary
A computing device for a multidimensional vector neural network includes: input lines to which multidimensional input vectors are input; output lines intersecting the input lines; memory cells disposed at intersecting points between the input lines and the output lines and configured to store weight elements included in multidimensional weight vectors; selectors configured to transmit a value output from each of the output lines to any one of adders; and the adders configured to accumulate values received from the selectors in a predetermined number of cycles, wherein, for each of the multidimensional weight vectors, weight elements included in the multidimensional weight vector are stored in reference memory cells that connect a corresponding single reference input line and corresponding two or more reference output lines.