Column Path Control Signal Circuit for PVT-Stable DRAM Timing
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Solution Overview
Problem
CMOS transistors in semiconductor devices, such as DRAMs, exhibit variations in process, voltage, and temperature (PVT) characteristics, leading to mismatched timings of column path control signals generated in parallel, resulting in erroneous read or write operations.
Innovation Solution
A circuit and method that utilize a strobe signal delay unit to generate delayed strobe signals with different delay periods, which are then processed by a control signal generator to produce column path control signals, ensuring these signals are influenced by the same PVT characteristics, thereby maintaining desired timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If column path control signals are generated in parallel through multiple delay units and inverters, then the signal generation speed is improved, but the timing coincidence of the signals deteriorates due to different PVT characteristic variations of CMOS transistors
Solution Approach 1:
The patent merges multiple independent delay units and inverters into a single integrated delay circuit that generates all column path control signals. By using one delay circuit instead of multiple separate units, all signals are subjected to the same PVT characteristic variations, ensuring their timings coincide properly while still achieving parallel signal generation.
Solution Approach 2:
The patent ensures homogeneity in the generation process by having all column path control signals pass through the same delay circuit architecture. This homogeneous approach ensures that all signals experience identical PVT characteristic variations, maintaining timing coincidence across different control signals.
2Adaptability or versatility
If multiple independent delay units are used to generate column path control signals, then the design flexibility is improved, but the manufacturing precision deteriorates due to PVT characteristic variations
Solution Approach 1:
The patent combines multiple delay functions into a single delay circuit that can generate various column path control signals with different timing requirements. This unified approach maintains design flexibility while ensuring all signals are affected equally by PVT variations, thereby improving timing accuracy.
3Productivity
If parallel processing of strobe signal is used to generate multiple control signals, then the productivity is improved, but the signal timing accuracy deteriorates due to different PVT variations
Solution Approach 1:
The patent merges the parallel processing functions into a single delay circuit that internally handles multiple signal generations. This approach maintains high productivity by generating multiple control signals simultaneously while ensuring they all experience the same PVT variations, thus preserving timing accuracy.
Data Source
AI summary
A circuit for generating column path control signals in a semiconductor device is provided. The circuit includes a strobe signal delay unit configured to receive a strobe signal, and delay the received strobe signal for different delay periods, to generate a plurality of respective delayed strobe signals, and a control signal generator configured to receive at least one of the delayed strobe signals, and perform a logical operation to the received signal, to generate a first column path control signal for controlling a column path of the semiconductor device.