Interleaved SEU-Tolerant Memory Cell Layout for Node Separation
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Solution Overview
Problem
CMOS memory cells face challenges in maintaining single-event upset (SEU) tolerance as design technology shrinks, leading to insufficient spacing between redundant nodes, which increases the vulnerability to ion hits and data corruption in smaller geometry ICs.
Innovation Solution
The implementation of interleaved memory cells, where portions of one memory cell are physically laid out between and adjacent to portions of another, providing increased separation between redundant nodes to enhance SEU tolerance without significantly increasing the chip area, even in designs below 90 nm technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cell design technology is shrunk to smaller geometry, then chip area is reduced, but spacing between redundant nodes becomes insufficient increasing vulnerability to ion hits
Solution Approach 1:
The memory cell is divided into two separate half-cells, each containing a portion of the redundant node pairs. This segmentation allows the half-cells to be interleaved with other memory cells while maintaining adequate spacing between redundant nodes within the same half-cell, thus preserving SEU tolerance in smaller geometries
Solution Approach 2:
The patent transitions from a conventional adjacent layout to an interleaved layout where half-cells are distributed throughout the memory array. This dimensional reorganization allows redundant nodes to maintain sufficient physical separation in the spatial domain, preventing simultaneous upset from ion hits while accommodating smaller geometry constraints
2Reliability
If redundant nodes are separated to improve SEU tolerance, then spacing between nodes increases, but chip area increases
Solution Approach 1:
Multiple half-cells are interleaved and merged into a unified memory array structure. By combining the spacing benefits of separated redundant nodes with the area efficiency of shared infrastructure (word lines, bit lines, and control circuits), the patent achieves SEU tolerance without proportionally increasing chip area
Solution Approach 2:
The interleaved half-cell structure serves multiple functions: it provides SEU tolerance through node separation, maintains area efficiency through shared memory array infrastructure, and enables scalable implementation across different technology nodes. The same structural approach benefits both reliability and area utilization
Data Source
AI summary
A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.