3D Memory Bit-Line Switching for Defective Cell Replacement
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Solution Overview
Problem
In three-dimensional semiconductor memory devices like DRAM, defective memory cells pose a challenge as they require replacement with redundant cells, but existing methods struggle to efficiently manage this process, particularly in hierarchical bit line structures.
Innovation Solution
A semiconductor memory device with a hierarchical bit line structure that includes a switching circuit and control circuit to selectively route data around defective cells, using redundant units to replace defective memory cells, ensuring reliable data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a hierarchical bit line structure is used to reduce bit line capacity, then sensing margin is improved, but managing defective cells becomes more complex
Solution Approach 1:
The bit line structure is segmented into hierarchical levels (global bit lines and local bit lines), allowing defective cells to be isolated at the local bit line level while maintaining efficient global signal routing. This segmentation enables selective replacement of defective cells without affecting the entire bit line structure, thus managing complexity while preserving sensing margin improvements.
2Reliability
If redundant cells are used to replace defective cells, then reliability is improved, but data loss may occur during the replacement process
Solution Approach 1:
The control circuit pre-identifies and stores the locations of defective cells before they affect data operations. By having replacement mappings prepared in advance, the system can switch to redundant cells without interrupting data retrieval or risking data loss during the replacement process.
Solution Approach 2:
The control circuit acts as an intermediary that manages the mapping between original bit line addresses and redundant bit line addresses. It translates address signals to route read/write operations through redundant cells when defects are detected, ensuring seamless data flow without direct intervention that could cause data loss.
3Reliability
If multiple defective cells exist across multiple bit lines, then more redundant cells are needed, but device complexity increases
Solution Approach 1:
The control circuit implements a universal address translation mechanism that handles multiple defective cells across different bit lines through a single integrated system. Rather than requiring separate replacement logic for each defective cell, the universal control circuit manages all redundant cell mappings centrally, reducing overall device complexity while maintaining comprehensive defective cell coverage.
Data Source
AI summary
A memory device includes memory cells, first wirings extending along a first direction and connected to the cells, second wirings extending along a second direction and connected to the cells, the second direction intersecting the first direction, third wirings extending along a third direction and each connected to one or more second wirings, the third direction intersecting the first and second directions, sense circuits each connected to one or more third wirings, a switching circuit connected to the circuits and selectively outputting signals from the sense circuits, and a control circuit storing first addresses indicating second and third wirings connected to defective cells, and when a memory cell is selected, determining second addresses indicating second and third wirings connected to the selected cell, and based on the first and second addresses, controlling the switching circuit not to output signals from one or more sense circuits connected to the defective cells.