DRAM Row Hammer Protection with ECC-Guided Targeted Refresh
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, face issues with data loss due to leakage currents and adjacent cell degradation from frequent word-line transitions, necessitating frequent refresh operations that increase power consumption and chip size overhead.
Innovation Solution
A semiconductor memory device with an error correction code (ECC) engine, error check and scrub (ECS) circuit, and row hammer management circuit that stores hammer addresses based on memory cell degradation, allowing for targeted refresh operations on intensively accessed rows, reducing unnecessary power consumption and chip size overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequent access is performed on certain memory cell rows, then data read performance is improved, but adjacent memory cells lose stored charges due to leakage current
Solution Approach 1:
The patent performs preliminary actions by monitoring access patterns and proactively identifying rows that are intensively accessed. The row hammer management circuit tracks access counts and compares them against reference values to predict which rows are likely to suffer from row hammer effects before significant data loss occurs. This allows the system to take preventive refresh actions on adjacent rows before the leakage current causes irreversible damage.
Solution Approach 2:
The patent implements feedback mechanisms through the row hammer management circuit that continuously monitors access patterns, counts the number of times each row is accessed, and uses this information to determine which rows need protective refresh operations. The circuit compares access counts against reference values and provides feedback to the refresh control circuit to adjust refresh strategies dynamically based on actual usage patterns.
2Reliability
If refresh operations are performed frequently to prevent data loss, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by performing refresh operations selectively only on rows that are identified as intensively accessed, rather than performing uniform refresh across all rows. The row hammer management circuit identifies specific rows with high access counts and directs refresh operations only to those rows and their adjacent rows, optimizing the balance between data retention and power consumption by avoiding unnecessary refresh operations on rarely accessed rows.
Solution Approach 2:
The patent changes the parameter of refresh operation frequency based on access pattern analysis. Instead of using a fixed refresh interval for all rows, the system dynamically adjusts refresh frequency based on the access count of each row. Rows with high access counts receive more frequent refresh operations, while rows with low access counts receive fewer or no refresh operations, optimizing power consumption while maintaining data retention.
3Reliability
If all memory cell rows are refreshed uniformly, then data retention is maintained, but unnecessary refresh operations increase power consumption
Solution Approach 1:
The patent implements local quality by differentiating refresh operations based on the specific characteristics of each row. The row hammer management circuit analyzes access patterns and identifies rows with high access counts that are prone to row hammer effects. The system then applies localized refresh strategies to only those rows and their adjacent rows, rather than uniformly refreshing all rows, thereby improving refresh operation efficiency by eliminating unnecessary operations.
Solution Approach 2:
The patent applies partial action by performing refresh operations only on the subset of rows that are most at risk from row hammer effects, rather than refreshing all rows. The row hammer management circuit identifies critical rows based on access patterns and directs refresh operations only to those rows and their adjacent rows, avoiding excessive refresh operations on rows that do not require protection.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an error check and scrub (ECS) circuit, a row hammer management circuit and a refresh control circuit. The ECC engine generates an error generation signal based on a result of an ECC decoding. The ECS circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. The row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.