Sense Amplifier Pre-Sensing with Offset Cancellation for DRAM
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Solution Overview
Problem
The significant difference in charge amounts between sensing bit lines and their complementary bit lines in volatile memory devices, such as DRAM, leads to decreased sensing sensitivity of the sense amplifier.
Innovation Solution
A sense amplifier with a shape-symmetric structure and operations including precharge, offset cancellation, charge sharing, pre-sensing, and restore operations, utilizing NMOS transistors, isolation/offset cancellation circuits, and equalization switches to equalize and sense voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional sense amplifier structure is used, then the device complexity is reduced, but the sensing sensitivity decreases due to significant charge differences between sensing bit line and complementary sensing bit line
Solution Approach 1:
The patent applies asymmetry by introducing different circuit configurations for the sensing bit line and complementary sensing bit line. Specifically, the sensing bit line includes a first sense amplifier with a first differential pair, while the complementary sensing bit line includes a second sense amplifier with a second differential pair that has different transistor sizing or connectivity. This asymmetric design allows the circuit to compensate for charge differences between the two lines, improving sensing sensitivity despite the increased structural complexity.
Solution Approach 2:
The patent introduces intermediate circuits including charge redistribution capacitors and isolation switches that act as mediators between the bit lines and sense amplifiers. These intermediary elements enable controlled charge transfer and isolation, allowing the sense amplifiers to operate with balanced charge conditions even when the original bit lines have significant charge differences, thereby improving sensing sensitivity without requiring complete redesign of the basic sense amplifier structure.
2Measurement precision
If charge amount difference between sensing bit line and complementary sensing bit line is large, then the circuit operation is simplified, but the sensing sensitivity decreases
Solution Approach 1:
The patent changes the electrical parameters of the bit lines by introducing charge redistribution capacitors connected to the sensing bit line and complementary sensing bit line. These capacitors allow dynamic adjustment of the charge levels on each line through controlled switching operations. By adjusting the capacitance values and switching timing, the circuit can equalize the charge amounts on both lines, improving sensing sensitivity while maintaining simplified circuit operation.
Solution Approach 2:
The patent performs preliminary charge equalization before the sensing operation by using isolation switches and charge redistribution capacitors to balance the charge amounts on the sensing bit line and complementary sensing bit line. This preliminary action ensures that both lines start with equal charge conditions, allowing the sense amplifiers to operate at optimal sensitivity without requiring complex real-time compensation during the sensing process itself.
3Measurement precision
If shape-symmetric structure with equalization switches is implemented, then sensing sensitivity is improved, but the device complexity increases
Solution Approach 1:
The patent implements equipotentiality by using equalization switches and charge redistribution capacitors to maintain equal charge levels (equipotential conditions) on the sensing bit line and complementary sensing bit line. The equalization switches are controlled to transfer charges between the lines until their potentials are equalized, creating a balanced starting condition for the sense amplifiers. This approach improves sensing sensitivity by ensuring symmetric operating conditions while adding manageable circuit complexity through the switch-capacitor network.
Data Source
AI summary
A sense amplifier which includes a sense amplifier circuit that includes a first NMOS transistor and a second NMOS transistor, the first NMOS transistor being connected to a first bit line and the second NMOS transistor being connected to a second bit line complementary to the first bit line, a first isolation/offset cancellation circuit that includes a first isolation switch connecting the first bit line and a first sensing bit line and a first offset cancellation switch connecting the first bit line and a second sensing bit line complementary to the first sensing bit line, and a second isolation/offset cancellation circuit that includes a second isolation switch connecting the second bit line and the second sensing bit line and a second offset cancellation switch connecting the second bit line and the first sensing bit line.