CoP Memory Core Layout for Faster Bitline Sensing in DRAM
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Solution Overview
Problem
Conventional DRAM devices face limitations in size reduction due to the arrangement of circuits for driving memory cell arrays, despite employing vertical channel transistors, as the efficient arrangement of bitlines and wordlines is challenging.
Innovation Solution
A memory core circuit with a cell on periphery (CoP) structure, where a core control circuit is disposed under a memory cell array, divided into sub peripheral circuits with specific regions for bitline sense amplifiers, wordline drivers, and rest regions containing device peripheral circuits, optimizing the layout to enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If vertical channel transistors are employed to reduce memory device size, then the feature size decreases, but the arrangement difficulty of driving circuits increases
Solution Approach 1:
The memory device is divided into multiple cell blocks, with each block containing its own dedicated driving circuits (sense amplifiers, wordline drivers). This segmentation allows independent optimization of each block's layout, simplifying the arrangement process while achieving overall size reduction through vertical channel transistors.
Solution Approach 2:
The patent transitions from planar driving circuit arrangement to a three-dimensional configuration by placing sense amplifiers and wordline drivers in vertical and lateral positions around the memory cell array. This multi-dimensional arrangement optimizes space utilization and reduces manufacturing complexity.
2Reliability
If open bitline structure is used with bitlines spread on both sides of sense amplifier, then sensing capability is maintained, but device size reduction is limited
Solution Approach 1:
The patent merges the functions of sense amplifiers and wordline drivers into integrated peripheral circuits that share common structures and processing steps. This consolidation reduces the overall device footprint while maintaining the open bitline sensing capability through optimized signal paths.
Solution Approach 2:
The sense amplifiers are positioned at specific locations within cell blocks, with bitlines configured to access them efficiently. This localized optimization allows compact arrangement while preserving sensing performance in critical regions.
3Productivity
If cell transistor size is reduced to increase integration density, then capacity increases, but implementation difficulty increases
Solution Approach 1:
The memory array is divided into multiple small cell blocks, each with standardized dimensions and components. This segmentation enables reduced cell transistor sizes while maintaining manufacturability through repetitive, standardized layouts that simplify fabrication processes.
Solution Approach 2:
The patent optimizes the physical parameters of cell transistors (channel width, length, spacing) to achieve higher integration density while staying within manufacturing capabilities. Vertical channel transistors are used to change the geometric parameters, allowing smaller footprint per cell.
Data Source
AI summary
A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits under the sub cell arrays. The sub peripheral circuits are divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are disposed in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region. At least a portion of device peripheral circuits configured to control the memory core circuit is disposed in a rest region other than the sense amplifier region and the wordline driver region.