SRAM Word-Line Pull-Down for Static Noise Margin Stability

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Solution Overview

Problem

SRAM cell design in deep submicron technologies faces challenges with variations in NMOS and PMOS device speeds, leading to reduced static noise margin (SNM), which can result in data corruption and performance degradation, especially at the Fast-Slow and Slow-Fast operation corners, making it difficult to maintain high cell density and speed advantages.

Innovation Solution

Incorporating a static noise margin (SNM) detector that controls a pull-down transistor to selectively couple or decouple the word line from the ground path, using a replica cell and shorted cell configuration to detect SNM events and increase the resistance of pass gates during WRITE operations, thereby enhancing SNM without degrading cell performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If SRAM cell size is reduced to increase cell density, then area is reduced, but static noise margin deteriorates

Engineering Contradiction:

Improvememory cell areaVSAvoidstatic noise margin

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The pull-down transistor is activated before the WRITE operation to pre-lower the word line voltage. This preliminary action increases the noise margin before the critical WRITE operation occurs, preventing data corruption without requiring larger cell dimensions

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The word line voltage is dynamically adjusted based on operational needs. During WRITE operations, the pull-down transistor activates to lower the word line voltage, increasing noise margin. During READ operations, the word line voltage returns to normal levels, maintaining standard performance characteristics

Inventive Principle:

Principle #15Dynamics

2Reliability

If word line voltage is lowered to increase noise margin, then static noise margin is improved, but WRITE operation speed deteriorates

Engineering Contradiction:

Improvestatic noise marginVSAvoidWRITE operation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The pull-down transistor is activated only during specific WRITE operations when noise margin is critical, not continuously. This periodic activation maintains high noise margin during vulnerable operations while preserving normal WRITE speed during other operations, avoiding continuous performance degradation

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The word line voltage parameter is changed dynamically based on operational context. During WRITE operations with potential noise susceptibility, the voltage is lowered to increase margin. The system adapts the voltage parameter in real-time to balance noise immunity and operation speed requirements

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7636268B1Integrated circuit with improved static noise margin

Publication Date: 2009.12.22 XILINX INC

AI summary

A static random access memory (“SRAM”) has a plurality of SRAM cells connected to a word line. A static noise margin (“SNM”) detector controls a pull-down transistor that selectively couples the word line to a ground path. The SNM detector is configured to produce a first output signal in response to a SNM event that couples the word line to the ground path, and otherwise produces a second output signal that de-couples the word line from the ground path.