Bitline Sense Amplifier With Sequential Boost Voltage Restoration
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Solution Overview
Problem
Existing memory devices face challenges in accurately restoring data to memory cells after a read operation due to fluctuations in cell capacitor charge, leading to potential data loss and reduced reliability.
Innovation Solution
A bitline sense amplifier is designed with a first and second switch circuit to control the supply of power and boost voltages to inverters, allowing for precise voltage control of bit lines, using a first boost voltage higher than a second power supply voltage and a second boost voltage lower than the second power supply voltage, enabling accurate data restoration and precharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional bitline sense amplifier is used for data restoration, then the circuit structure is simple, but the voltage control precision is insufficient leading to restoration errors
Solution Approach 1:
The sense amplifier is divided into multiple independent inverter stages (first inverter, second inverter, third inverter) with separate control mechanisms. Each inverter stage can be independently controlled through dedicated switch circuits, allowing precise voltage control at each stage while maintaining modular simplicity in the overall structure.
Solution Approach 2:
The patent implements dynamic voltage control by sequentially applying different voltages (first voltage, second voltage, third voltage) to the bitline at different restoration stages. The switch circuits dynamically transition between these voltage levels based on restoration progress, enabling adaptive voltage control that optimizes both precision and efficiency.
2Reliability
If multiple voltage levels are applied to restore data accurately, then the restoration accuracy is improved, but the control complexity increases
Solution Approach 1:
The switch circuits are pre-configured with predetermined voltage levels (first voltage for initial restoration, second voltage for intermediate stage, third voltage for final stage). This preliminary setup allows the restoration process to proceed through predetermined voltage sequences without requiring complex real-time decision logic, simplifying control while ensuring accurate restoration.
Solution Approach 2:
The data restoration process is divided into periodic stages, with each stage applying a specific voltage level for a predetermined time period. The switch circuits sequentially activate different voltage levels in a periodic manner, allowing the bitline to stabilize at each voltage stage before transitioning to the next, thereby improving restoration reliability without requiring complex continuous control.
3Measurement precision
If sequential voltage application is used for bitline control, then the voltage setting accuracy is improved, but the operation time increases
Solution Approach 1:
The switch circuits are designed to seamlessly transition between different voltage levels without interruption. The second switch circuit maintains continuous connection to the bitline throughout the restoration process, ensuring that the useful action of voltage application continues uninterrupted while the voltage level changes, thereby minimizing time loss while maintaining voltage setting accuracy.
Solution Approach 2:
The patent applies voltages that are slightly higher or lower than the ideal target voltage levels (excessive action) to ensure rapid and accurate voltage setting. By applying the first voltage that may exceed the target voltage and then quickly transitioning to the second and third voltages, the system ensures accurate final voltage setting while minimizing the time required for each transition stage.
Data Source
AI summary
A bitline sense amplifier includes an amplifier circuit having a plurality of PMOS elements and a plurality of NMOS elements, a first switch circuit supplying a first power supply voltage to the plurality of PMOS elements, and a second switch circuit supplying one of a second power supply voltage, lower than the first power supply voltage, a first boost voltage higher than the second power supply voltage, and a second boost voltage, lower than the second power supply voltage, to the plurality of NMOS elements. The second switch circuit sequentially applies the first boost voltage, the second boost voltage, and the second power supply voltage to the plurality of NMOS elements based on an execution of a read operation.