Shift Register Flip-Flop Gating for Lower Power Consumption
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Solution Overview
Problem
Conventional shift registers in data drivers experience unnecessary power consumption as all flip-flops work simultaneously, regardless of their necessity, leading to inefficiency.
Innovation Solution
A flip-flop design where the flop core only works when either the input signal or the fed-back output signal is enabled, allowing only the necessary flip-flops to operate and reducing power consumption by disabling the flop core when both signals are disabled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If all flip-flops work simultaneously in a conventional shift register, then the data signal can be transmitted through all stages, but the power consumption increases unnecessarily
Solution Approach 1:
The patent applies dynamics by making the operation of each flip-flop stage conditional and variable rather than static and continuous. The flop core of each flip-flop is controlled to work or stop based on the state of its input and output signals. Specifically, when both the input signal and fed-back output signal are disabled, the flop core stops working; when at least one is enabled, the flop core works. This dynamic control ensures that only necessary stages are active during data transmission, reducing power consumption while maintaining reliable data signal transmission through the shift register.
Solution Approach 2:
The patent applies local quality by making each flip-flop stage have different operational states based on its local signal conditions. Instead of all stages operating uniformly, each flop core independently determines whether to work or stop based on its own input and output signal states. This localized control allows only the specific stages that are currently receiving or generating enabled data signals to consume power, while other stages remain inactive, thereby resolving the contradiction between power consumption and data transmission reliability.
2Use of energy by stationary object
If the flop core stops working when both input and output signals are disabled, then power consumption is reduced, but the flip-flop must quickly resume operation when needed
Solution Approach 1:
The patent applies preliminary action by maintaining the structural integrity and signal path readiness of the flop core even when it is in the stopped state. The flop core is designed to be in a standby condition where it can quickly transition from stopped to working state when the input or output signal becomes enabled. The control logic that monitors the input and output signal states is continuously active, so it can immediately detect when resumption of operation is needed and activate the flop core without delay, thus achieving both power savings and fast response.
Solution Approach 2:
The patent applies periodic action through the cyclic monitoring of signal states and the corresponding periodic activation/deactivation of the flop core. The flop core operates in a rhythm dictated by the data signal flow - it works when needed and stops when not needed, creating a periodic pattern of operation that adapts to the actual data transmission requirements. This periodic control mechanism ensures that the flop core responds quickly to changes in signal states while minimizing unnecessary operation and power consumption.
Data Source
AI summary
A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.