Memory Delay Circuit Bias Control for Stable tRCD Sensing
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining a consistent sensing margin time due to process, voltage, and temperature variations, which can lead to incorrect data amplification and reduced operating speed.
Innovation Solution
A delay circuit is introduced that includes a current source controlled by a bias voltage, with a delay time adjusted based on the current amount, and a bias voltage generating unit that divides the power supply voltage using resistors to ensure a constant delay time, thereby stabilizing the sensing margin time despite variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional delay circuit is used, then the circuit structure is simple, but the delay time varies due to process, voltage, and temperature variations
Solution Approach 1:
The patent changes the bias voltage parameter dynamically to compensate for delay time variations. The bias voltage generating unit adjusts the bias voltage based on detected delay time deviations, thereby maintaining consistent delay performance despite PVT variations. This parameter adjustment approach resolves the contradiction by using a controllable parameter (bias voltage) to stabilize the delay time without fundamentally changing the circuit topology.
Solution Approach 2:
The patent implements a feedback mechanism where the delay time is detected and used to adjust the bias voltage. The bias voltage generating unit receives feedback about the actual delay time and modifies the bias voltage accordingly to maintain the target delay time. This closed-loop feedback system resolves the contradiction by continuously correcting delay variations without requiring a completely complex circuit redesign.
2Reliability
If the sensing margin time is too short, then the operating speed is fast, but incorrect data amplification occurs
Solution Approach 1:
The patent adjusts the bias voltage parameter to precisely control the delay time of the sensing margin time generation circuit. By optimizing the bias voltage, the circuit achieves the minimum required sensing margin time for reliable data amplification while minimizing the time duration, thereby balancing reliability and operating speed. This parameter optimization resolves the contradiction between adequate sensing time and fast operation.
3Reliability
If the delay time is adjusted to compensate for variations, then the sensing margin time consistency is improved, but additional control circuits are required
Solution Approach 1:
The bias voltage generating unit serves multiple functions: it generates the bias voltage for the delay circuit, detects the actual delay time, and adjusts the voltage to compensate for variations. By combining these functions in a single integrated unit, the patent achieves reliable sensing margin time consistency without proportionally increasing circuit complexity. This multi-functionality approach resolves the contradiction by maximizing the utility of added circuit elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution secures a constant sensing margin time, ensuring accurate data amplification within a preset RAS to CAS delay, enhancing the operational precision and speed of semiconductor memory devices.
Implementation Method 1
a bias voltage generating unit configured to divide a power supply voltage using a first resistor to generate the bias voltage
Implementation Method 2
a delay unit including a current source controlled by a bias voltage, a delay time of the delay unit being changed depending on current amount of the current source
Data Source
AI summary
A delay circuit is capable of securing a constant delay time in spite of a process variation as well as voltage and temperature variations. Using the delay circuit that secures a sensing margin time in spite of process, voltage and temperature variations, a semiconductor memory device is capable of amplifying desired data within a preset RAS to CAS delay (tRCD). The delay circuit includes a delay unit including a current source controlled by a bias voltage, a delay time of the delay unit being changed depending on current amount of the current source, and a bias voltage generating unit configured to divide a power supply voltage using a first resistor to generate the bias voltage, wherein the delay unit includes a second resistor inserted into a current path of the current source.