SRAM Sub-Array Architecture for Deterministic In-Memory Computing
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Solution Overview
Problem
Analog in-memory compute operations face issues such as inadvertent bit flips, non-deterministic computations, and complex circuitry, making them unsuitable for safety-critical applications.
Innovation Solution
A memory architecture that supports both conventional memory access and digital in-memory computation modes, utilizing a SRAM array segmented into sub-arrays, with a control circuit to switch between modes, enabling parallel access and deterministic computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If analog in-memory compute operations are used, then computational efficiency is improved, but reliability deteriorates due to inadvertent bit flip and analog signal level variations
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each capable of independent operation. This segmentation allows selective activation of sub-arrays based on computational needs, enabling deterministic digital operations in specific regions while maintaining analog compute capabilities in others, thus resolving the reliability-efficiency contradiction.
Solution Approach 2:
The system dynamically switches between analog in-memory compute mode and digital readout mode based on operational requirements. The row decoder circuit can selectively actuate word lines to enable either wide vector access for analog computation or precise single-row access for digital operations, providing adaptive reliability for different computational tasks.
2Reliability
If conventional memory access mode is used, then reliability is maintained, but productivity deteriorates due to limited access speed
Solution Approach 1:
The memory circuit is designed to support multiple operational modes including conventional memory access mode and analog in-memory compute mode. The same memory array and control circuitry can be configured for either high-reliability conventional access or high-speed analog computation, eliminating the need for separate dedicated circuits for each function.
3Productivity
If wide vector access is implemented for digital in-memory computation, then productivity is improved, but device complexity increases due to control circuit requirements
Solution Approach 1:
The row decoder circuit automatically configures its operation based on the operational mode. In digital in-memory compute mode, it automatically enables wide vector access by simultaneously actuating multiple word lines. The control logic self-adjusts the decoding behavior without requiring external complex control mechanisms, simplifying the overall system architecture.
Data Source
AI summary
The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.