DRAM Refresh Address Circuit for Same-Bank Row Refresh
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) technologies face challenges in efficiently generating refresh addresses for same bank refresh mode, where the same bank in different bank groups are simultaneously refreshed row by row, leading to issues with address generation and storage.
Innovation Solution
A refresh address generation circuit comprising a refresh control circuit and an address generator that sequentially processes refresh commands, outputting clock signals based on preset conditions to manage address changes, ensuring efficient address generation for both same bank and all bank refresh modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional address generation circuit is used, then the circuit structure is simple, but the refresh address cannot be updated in real-time and requires full screen refresh
Solution Approach 1:
The address generation circuit is segmented into multiple independent modules: a refresh address generator that produces row address counters, a column address generator that produces column address counters, and a memory controller that coordinates them. This segmentation allows each module to operate independently and update addresses in real-time without requiring full screen refresh, thereby improving refresh speed while keeping individual module complexity manageable.
Solution Approach 2:
The refresh address generator pre-generates row address counter values and the column address generator pre-generates column address counter values before they are needed for actual memory access. This preliminary generation of address sequences enables the system to update refresh addresses in real-time without waiting for frame completion, resolving the contradiction between fast refresh and circuit complexity.
2Productivity
If frame synchronization signal is used for address generation, then the address generation is synchronized, but the refresh rate is limited and cannot achieve high refresh rates
Solution Approach 1:
The invention implements periodic refresh actions at multiple nested levels: a vertical refresh rate of 60Hz for full screen updates, and a horizontal refresh rate of 8000Hz for line-by-line updates within each frame. This multi-level periodic action allows the system to maintain high overall refresh rates while still providing synchronized address generation, overcoming the limitation of single-rate frame synchronization.
Solution Approach 2:
The address generation system dynamically adjusts between frame-synchronized mode for full refresh and line-synchronized mode for incremental updates. The memory controller dynamically selects between generating addresses based on vertical frame boundaries or horizontal line boundaries, enabling the system to achieve high refresh rates for partial updates while maintaining synchronization when needed, thus resolving the contradiction between refresh rate and synchronization duration.
3Loss of energy
If incremental refresh is used, then power consumption is reduced, but image quality deteriorates due to missed refresh lines
Solution Approach 1:
The system implements feedback mechanisms where the memory controller monitors which memory lines have been refreshed and uses this information to determine the next refresh sequence. This feedback ensures that incremental refresh operations maintain image quality by systematically covering all lines over time while minimizing power consumption, preventing the image quality deterioration that occurs in simple incremental refresh schemes.
Solution Approach 2:
The invention discards the conventional approach of refreshing entire frames and instead recovers energy by selectively refreshing only the memory lines that need updating. The system tracks refresh status and recovers power by avoiding redundant refresh operations on already-updated lines, while maintaining complete image coverage through systematic progression through all memory lines, thus resolving the contradiction between power saving and image quality.
Data Source
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AI summary
The present invention relates to the technical field of semiconductors, and in particular, to a refresh address generation circuit and method, a memory, and an electronic device. The refresh address generation circuit includes a refresh control circuit and an address generator. The refresh control circuit is configured to sequentially receive multiple first refresh commands and perform first refresh operations respectively; output a first clock signal under a condition that the number of the first refresh operations is less than a preset value or output a second clock signal under a condition that the number of the first refresh operations is equal to the preset value n, where n is a positive integer greater than or equal to 1. The address generator is coupled to the refresh control circuit, pre-stores a first address, receives the first clock signal or the second clock signal, and outputs a first to-be-refreshed address in response to the first clock signal during each of the first refresh operations. The first to-be-refreshed address includes the first address. The address generator changes the first address in response to the second clock signal. A refresh address refreshed by a same bank can be provided.