Serial Peripheral Interface Multi-I/O Reads for Faster Flash Access
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Solution Overview
Problem
Conventional serial flash memory devices transfer data or address bits sequentially, limiting their speed and efficiency in data transfer operations.
Innovation Solution
The method and system for a serial peripheral interface protocol in integrated circuits enable dual I/O or quadruple I/O data read operations by using multiple pins to transmit address and data bits concurrently, reducing clock cycles and enhancing data transfer rates through configurable wait cycles and edge-triggered transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data or address bits are transferred sequentially in conventional serial flash memory devices, then the pin count is reduced, but the data transfer speed is limited
Solution Approach 1:
The patent transitions from sequential single-bit transfer to parallel multi-bit transfer by utilizing multiple I/O pins (dual I/O, quadruple I/O) within the serial peripheral interface framework. This dimensional change from 1D sequential to 2D parallel architecture enables simultaneous transmission of multiple address and data bits, directly resolving the speed limitation while preserving the low pin-count advantage of serial interfaces
Solution Approach 2:
The patent segments the data and address bus into multiple parallel channels using separate I/O pins (e.g., SIO0, SIO1, SIO2, SIO3). By dividing the transfer operation across multiple segmented paths that can operate concurrently, the system achieves higher throughput while maintaining the serial peripheral interface's compact pin structure
2Device complexity
If sequential transfer method is used, then device complexity is reduced, but productivity is limited
Solution Approach 1:
The patent implements continuous parallel data flow across multiple I/O pins during read and write operations. By enabling simultaneous transmission on multiple channels without sequential waiting, the system maximizes the continuity of useful action, thereby significantly improving productivity and data transfer rate while keeping the transfer mechanism relatively simple through standardized SPI-compatible signaling
3Speed
If concurrent address and data transfer is implemented, then data transfer rate is improved, but device complexity increases
Solution Approach 1:
The patent extends the universal serial peripheral interface protocol to support multiple I/O pins with unified signaling conventions. The same SPI-compatible clocking, sampling, and control mechanisms are applied across all I/O channels, allowing concurrent address and data transfer without requiring separate complex control logic for each pin. This multi-functionality approach enables high-speed parallel operation while maintaining relatively simple interface configuration
Data Source
AI summary
An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface supports an address of a second configuration upon receipt of a second command, the second configuration being different from the first configuration. In a specific embodiment, the first and the second configurations are different in address length. In another embodiment, a second address cooperated with the second command has a first part and a second part, the second part comprising a plurality of byte addresses, each of the byte addresses being associated with a corresponding byte of data. In another embodiment, integrated circuit device also includes a mode logic circuit for controlling operations of the first command and the second command. Various other embodiments are also described.