Sense Amplifier Flip-Flop Timing for Lower Output Delay
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Solution Overview
Problem
Conventional sense amplifier-based flip-flops face challenges in reducing output delay time while maintaining input sensitivity, often resulting in increased data loss and operation errors due to decreased input sensitivity caused by the use of current passing units.
Innovation Solution
The implementation of first and second current passing units with different clock signal delays, controlled by clock signal slope controllers, to pass current from specific nodes to ground terminals based on logic levels, thereby reducing output delay time and enhancing input sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If current passing units are used in conventional sense amplifier-based flip-flops, then output delay time is reduced, but input sensitivity decreases causing data loss and operation errors
Solution Approach 1:
The current passing function is segmented into two separate units (first current passing unit and second current passing unit), each controlled by clock signals with different delays. This segmentation allows independent optimization of each unit's operation timing, reducing overall output delay while maintaining input sensitivity through coordinated operation.
Solution Approach 2:
The first current passing unit is activated earlier (with first delay) than the second current passing unit (with second delay), where first delay < second delay. This preliminary action allows the first unit to begin reducing output delay before the second unit activates, optimizing the timing sequence to minimize total delay while preserving sensitivity.
2Loss of time
If single clock signal timing is used, then circuit complexity is reduced, but output delay time cannot be optimized without affecting input sensitivity
Solution Approach 1:
The system transitions from static single-clock control to dynamic multi-clock control, where two clock signals with different delay characteristics are applied to different current passing units. This dynamic timing control enables optimization of output delay time while maintaining input sensitivity, as each unit operates at optimally timed moments.
Solution Approach 2:
The invention changes the timing parameter of clock signals applied to different current passing units. By applying clock signals with different delays (first delay ≠ second delay), the system optimizes the operational timing of each current passing unit, thereby reducing output delay time while maintaining input sensitivity through parameter differentiation.
Data Source
AI summary
A sense amplifier based flip flop and method thereof are provided. The example sense amplifier-based flip-flop may include a first current passing unit receiving a first clock signal with a first delay, the first current passing unit configured to pass current from a first node to a ground terminal if the applied first clock signal is set to a first logic level and not to pass current from the first node to the ground terminal if the applied first clock signal is set to a second logic level and a second current passing unit receiving a second clock signal with a second delay, the second delay and the first delay not being the same, the second current passing unit configured to pass current from a second node to the ground terminal if the applied second clock signal is set to the first logic level and not to pass current from the second node to the ground terminal if the applied second clock signal is set to the second logic level.