Small Clock Buffer Control for Memory Power-Down Timing
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Solution Overview
Problem
Conventional semiconductor memory devices experience failures or defects in clock pulse generation due to improper control of clock buffers during power-down and self-refresh modes, particularly when the LAS idle signal is high, leading to incorrect clock enable signal states and missed clock pulses.
Innovation Solution
Incorporating a small clock buffer that is controlled independently of the main clock buffer, using a clock enable controller to synchronize internal clock enable signals with a small clock signal, and a clock controller to manage enable signals based on specific conditions, ensuring proper timing and preventing erroneous clock pulse generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock buffer is used to control clock signals during power-down and self-refresh modes, then device complexity is reduced, but reliability deteriorates due to incorrect clock pulse generation
Solution Approach 1:
The clock buffer control is segmented into two independent buffers: a main clock buffer for normal operation and a small clock buffer for power-down and self-refresh modes. This segmentation allows each buffer to be optimized for its specific operating mode, preventing the clock pulse generation defects that occur when a single buffer attempts to handle all modes.
Solution Approach 2:
The system dynamically switches between the main clock buffer and the small clock buffer based on the operating mode. The clock enable controller activates the appropriate buffer depending on whether the device is in normal operation, power-down, or self-refresh mode, ensuring reliable clock pulse generation across all conditions.
2Use of energy by moving object
If the clock buffer is turned off during power-down mode to reduce power consumption, then energy efficiency is improved, but clock signal timing control deteriorates
Solution Approach 1:
The clock buffering function is segmented into two separate buffers with different power management characteristics. The small clock buffer is specifically designed to remain active during power-down mode to maintain proper timing control, while the main clock buffer can be fully turned off to maximize power savings.
Solution Approach 2:
The clock enable controller acts as an intermediary that manages the power states of both clock buffers. It ensures that the small clock buffer remains operational during power-down mode to maintain timing accuracy, while allowing the main clock buffer to be powered down for energy efficiency.
3Reliability
If the clock enable signal is delayed to secure setup hold time, then timing safety is improved, but clock pulse generation timing deteriorates during mode transitions
Solution Approach 1:
The clock enable signal path is segmented into separate delay control mechanisms for the main clock buffer and the small clock buffer. This allows the delay to be optimized for setup hold time compliance in normal operation, while preventing excessive delays during power-down mode transitions when the small clock buffer is active.
Data Source
AI summary
A semiconductor memory device includes a clock enable buffer; a clock enable controller; a clock controller; a clock buffer; and a small clock buffer. The clock enable buffer buffers a clock enable signal to provide an internal clock enable signal. The clock enable controller synchronizes the internal clock enable signal with a small clock signal to output a first and a second signal. The clock controller generates a clock buffer enable signal and a small clock buffer enable signal based on the first and the second signals. The clock buffer is driven in response to the clock buffer enable signal and buffers a clock to produce a clock pulse. The small clock buffer is driven in response to the small clock buffer enable signal and buffers the clock to produce the small clock signal.