Multiplexed Pipeline Cache Memory for Two-Cycle Low-Latency Reads
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Solution Overview
Problem
Conventional microprocessor caches using SRAM face high latency and increased power consumption due to leakage currents, limiting operating speed and efficiency.
Innovation Solution
A low-latency multiplexed pipeline memory system with alternating read operations between two banks of bitcells, utilizing self-timed clock signals and a bank multiplexer to reduce latency to two cycles, thereby reducing power consumption and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM caches are used for high-speed data storage, then processing speed is improved, but power consumption increases due to leakage currents
Solution Approach 1:
The cache memory is divided into multiple banks (first bank, second bank, third bank, fourth bank) that can operate independently. This segmentation allows the system to alternate between banks, enabling one bank to be accessed while another is in standby mode with reduced power consumption, thus resolving the contradiction between maintaining high-speed access and reducing leakage current power consumption.
Solution Approach 2:
The system implements periodic alternating access between different cache banks using a bank select signal that changes state with each access cycle. This periodic switching allows banks to enter low-power standby modes between accesses, reducing overall power consumption while maintaining the appearance of continuous high-speed operation to the processor.
2Speed
If SRAM caches are used for high-speed data storage, then processing speed is improved, but device complexity increases due to numerous transistors per bit
Solution Approach 1:
By segmenting the cache into multiple banks, the system can share certain circuitry (such as read amplifiers and control logic) across banks, reducing the total transistor count compared to a single large cache. The segmentation allows for more efficient resource utilization and reduced redundancy in circuit implementation.
3Speed
If read operations are performed on cache banks, then data access speed is improved, but latency increases due to operation duration
Solution Approach 1:
The cache is divided into multiple banks that can be accessed in an interleaved manner. While one bank is undergoing a read operation, another bank can simultaneously service an access request. This bank-level segmentation effectively hides the latency of individual read operations, maintaining high data access speed while reducing perceived latency through parallel bank operation.
Solution Approach 2:
The system maintains continuous useful action by alternating between banks during read operations. When one bank is busy with a read operation, the system can immediately service another request on a different bank, ensuring that the cache as a whole remains continuously productive and minimizing idle time, thus reducing effective latency.
Data Source
AI summary
A memory such as for a high-speed microprocessor cache includes a first bank of bitcells and a second bank of bitcells. The banks are read from in a pipelined fashion with respect to cycles of a system clock signal such that a first read operation to the first bank is initiated with respect to a first cycle of the system clock signal whereas a second read operation to the second bank is initiated with respect to a second cycle of the system clock that is consecutive to the first clock cycle. A multiplexer selects between latched bits from the read operations responsive to cycles of the system clock signal.