In-Memory Current Reading Circuit Without ADC Conversion Bottlenecks
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Solution Overview
Problem
The existing ADCs in in-memory computation devices have a high die occupation area and slow conversion time, leading to high manufacturing costs and low performance in in-memory computation devices.
Innovation Solution
The in-memory computation device employs a word line activation unit, a memory array, and a digital detector with an integration stage and a counter stage to process input values, integrating the bit line current and a digital detector with an integration stage and a counter stage to perform successive sampling iterations, integrating the bit line current and updating the output signal based on sampling thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog-to-digital converters (ADCs) are used in known in-memory computation devices, then current reading and data processing can be performed, but die occupation area increases and conversion time slows down
Solution Approach 1:
The patent extracts the ADC function from the traditional reading circuit and replaces it with a digital detector that directly counts memory cell states. This removes the bulky ADC component while maintaining the ability to read and process computation results, thereby reducing die occupation area while preserving measurement precision.
Solution Approach 2:
The patent replaces the analog-to-digital conversion mechanism with a direct digital detection mechanism. Instead of using analog ADC circuits to convert current signals to digital values, the system uses a digital detector to directly sense and count the states of memory cells, substituting a complex analog conversion system with a simpler digital detection approach.
2Measurement precision
If analog-to-digital converters (ADCs) are used in known in-memory computation devices, then current reading can be performed, but conversion time increases and performance decreases
Solution Approach 1:
By removing the ADC component entirely and replacing it with a digital detector that directly counts memory cell states, the patent eliminates the time-consuming analog-to-digital conversion process. The digital detector can immediately sense and process computation results, significantly reducing conversion time while maintaining the precision needed for accurate reading.
Solution Approach 2:
The patent enables continuous operation by eliminating the sequential analog-to-digital conversion bottleneck. The digital detector can continuously and simultaneously detect the states of multiple memory cells without the time delays inherent in ADC conversion processes, allowing for faster and more efficient computation performance.
3Measurement precision
If ADCs with high precision are used, then measurement accuracy is maintained, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent extracts and removes the complex ADC subsystem from the reading circuit. By replacing it with a simple digital detector that directly counts memory cell states, the device complexity is dramatically reduced. This simpler architecture is easier to manufacture and less costly while preserving the ability to achieve high measurement accuracy through direct digital sensing.
Solution Approach 2:
The patent employs a simple, low-cost digital detector instead of expensive, complex ADC circuits. The digital detector uses basic digital logic elements that are cheaper and easier to manufacture than precision ADC components, reducing both device complexity and manufacturing costs while maintaining sufficient measurement accuracy for the application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces die area occupancy, lowers manufacturing costs, and enables fast computation times with high measurement accuracy and low power consumption.
Implementation Method 1
the memory cells being configured to be flown through each by a respective cell current that is a function of the respective activation signal and the respective computational weight
Implementation Method 2
the bit line being configured to be flown through by a bit line current that is a summation of the cell currents
Data Source
AI summary
A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.