Memory Cell Block Logic Circuit With Rewritable Truth Tables
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Solution Overview
Problem
Existing semiconductor devices that operate memory as a logic circuit face challenges such as the need for rewiring when truth values are rewritten and difficulty in data feedback, as well as suboptimal memory cell block scaling.
Innovation Solution
A semiconductor device with multiple memory cell blocks, each having three or more inputs and outputs, equipped with two readout address decoders and connected in a configuration that allows truth table data to be rewritten without rewiring and enables data feedback, optimizing the scale of memory cell blocks for logic circuit operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If truth values in memory are rewritten, then logic circuit functionality can be updated, but wiring reconnection is needed
Solution Approach 1:
The patent divides the memory into multiple memory cell blocks (first, second, third, and fourth blocks) with specific connectivity patterns. Each block can be independently configured through truth table data without affecting the physical wiring structure. This segmentation allows functionality updates by rewriting truth values in specific blocks while maintaining fixed wiring connections.
Solution Approach 2:
The patent enables dynamic reconfiguration of logic circuit functionality through voltage application to word lines. By selectively applying voltages to different word lines (W0-W7) in different memory cell blocks, the system can dynamically switch between different logic operations without physical wiring changes. The truth table data stored in each block determines the logic function based on which word lines are activated.
2Ease of manufacture
If memory cell blocks are arranged in arrayed manner with limited outputs, then manufacturing is simplified, but data feedback capability is lost
Solution Approach 1:
The patent creates an asymmetric connectivity pattern where memory cell blocks have different input-output relationships. Specifically, the first memory cell block receives inputs from external terminals and feeds output to the second block, while the third block feeds back to the first block through the fourth block. This asymmetric arrangement enables data feedback loops while maintaining a regular arrayed structure that is manufacturable.
Solution Approach 2:
The patent explicitly implements feedback by connecting the output of the third memory cell block back to the input of the first memory cell block through the fourth block. This creates a closed-loop system where data can circulate through multiple cycles, enabling sequential logic operations and state retention without requiring additional feedback wiring outside the memory array structure.
3Speed
If multiple readout word lines are applied, then data reading speed is improved, but power consumption increases
Solution Approach 1:
The patent employs partial action by selectively activating only the necessary word lines required for the current logic operation. Instead of applying voltage to all readout word lines simultaneously, the system activates only those word lines that correspond to the current truth table configuration and input data pattern. This reduces power consumption while maintaining fast reading speed by avoiding unnecessary memory cell access.
Data Source
AI summary
A semiconductor device comprises multiple memory cell blocks including multiple memory cells for storing a predetermined amount of data. Each of the memory cell blocks having three or more inputs and three or more outputs includes two readout address decoders as to the memory cells internally, stores truth table data for outputting a desired logical value as to predetermined address input, and is configured so as to operate as a logic circuit. Also, the memory cells include two readout word lines corresponding to the two readout address decoders, and in the case of the voltage of both of the two readout word lines being applied, the data held at this time is read out from readout data lines. Further, between the memory cell blocks is connected such that the three or more outputs from one memory cell block are input to three or more other memory cell blocks.