Multi-Layer Gate Structure With Protective Sidewalls for DRAM Scaling
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Solution Overview
Problem
Existing semiconductor devices face challenges in reliably and stably forming elements with decreased sizes while maintaining performance, particularly in dynamic random access memory (DRAM) applications.
Innovation Solution
The semiconductor device incorporates a gate structure with a specific configuration, including a gate electrode composed of multiple conductive patterns and protective layers with distinct materials, and spacer structures to enhance stability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a gate electrode with decreased size is formed to improve device scaling, then productivity and device density are improved, but manufacturing precision and reliability deteriorate due to difficulties in reliably forming smaller elements
Solution Approach 1:
The gate electrode is divided into three distinct conductive patterns (lower, intermediate, and upper) with different materials and functions. This segmentation allows each layer to be optimized independently for its specific role, improving overall manufacturing precision while maintaining small device dimensions. The lower conductive pattern provides work function control, the intermediate pattern provides structural support, and the upper pattern provides low resistance, with each layer formed using tailored processes.
Solution Approach 2:
Different portions of the gate electrode are made from different materials with different properties. The lower conductive pattern uses materials optimized for work function control (e.g., tungsten silicide, titanium nitride), the intermediate pattern uses polysilicon for structural stability, and the upper pattern uses low-resistance materials (e.g., copper, cobalt). This local differentiation enables precise control over electrical characteristics at each location, improving manufacturing reliability.
2Reliability
If a protective layer with different materials is applied to protect the gate electrode during etching, then reliability is improved, but device complexity increases
Solution Approach 1:
The protective layer is configured with different materials at different locations: a first protective material (e.g., silicon nitride) contacts the lower and intermediate conductive patterns, while a second protective material (e.g., silicon oxide) contacts the upper conductive pattern. This local differentiation provides targeted protection where needed during etching processes without requiring a completely complex multi-layer structure throughout the entire device.
Solution Approach 2:
The protective layer acts as an intermediary between the gate electrode and the etching environment. By placing materials with appropriate etch selectivity between the gate electrode structures and the etching chemistry, the protective layer shields sensitive conductive patterns from damage while allowing the etching process to proceed on other structures.
3Reliability
If multiple conductive patterns with different materials are used in the gate electrode, then electrical characteristics are improved, but manufacturing precision deteriorates due to complexity in forming multiple layers
Solution Approach 1:
The gate electrode is segmented into three formable layers (lower, intermediate, upper) that can be deposited and patterned using standard semiconductor fabrication techniques. Each layer is formed with controlled thickness and material composition, allowing precise control over the final electrical characteristics while using established manufacturing processes for each individual layer.
Solution Approach 2:
The gate electrode uses a composite structure combining multiple materials (e.g., tungsten silicide/titanium nitride in the lower pattern, polysilicon in the intermediate pattern, and copper/cobalt in the upper pattern). This composite approach allows optimization of electrical properties (work function, resistance, capacitance) while each material layer can be formed using its own optimized deposition and patterning processes.
Data Source
AI summary
A semiconductor device includes an active region, a gate dielectric layer disposed on the active region, a gate electrode disposed on the gate dielectric layer, a protective layer in contact with a portion of a side surface of the gate electrode, and a spacer structure covering the side surface of the gate electrode and the protective layer. The gate electrode includes a lower conductive pattern disposed on the gate dielectric layer, an intermediate conductive pattern disposed on the lower conductive pattern, and an upper conductive pattern disposed on the intermediate conductive pattern. The protective layer includes a first protective portion in contact with at least a portion of a side surface of the intermediate conductive pattern and a second protective portion in contact with a side surface of the upper conductive pattern, and the second protective portion includes a material different from a material of the first protective portion.