Programmable Linear Receiver Stages for DDR DQS-DQ Skew Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computer systems, the skew of data signals (DQ) relative to the clock/strobe signal (DQS) from DDR2/DDR3 memory devices can lead to difficulties in clocking all data signals effectively, limiting the maximum DDR operating speed due to increased likelihood of sampling DQ signals during transition between valid states.
Innovation Solution
A receiver architecture for computer processors that includes multiple linear receiver stages and a programming architecture to transform and align differential DQS and DQ signals, generating a clock signal with transition edge timing to sample DQ signals when they are well-settled, thereby reducing signal skew and maximizing DDR speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the DQ signals are transmitted over long distances in DDR systems, then data transfer capability is improved, but signal skew increases causing alignment errors
Solution Approach 1:
The receiver is divided into multiple independent stages (first linear receiver stage, second linear receiver stage, third linear receiver stage) that process signals sequentially. Each stage can be independently configured to compensate for different portions of the skew, allowing the system to maintain signal alignment over long transmission distances without sacrificing data transfer capability.
Solution Approach 2:
The receiver stages incorporate programmable voltage swings and delays that can be dynamically adjusted based on the actual signal conditions. This dynamic configuration allows the system to adapt to varying skew conditions and maintain optimal signal alignment while supporting high data transfer rates in DDR systems.
2Productivity
If the operating speed is increased to maximize productivity, then data transfer rate improves, but the likelihood of sampling DQ signals during transition increases
Solution Approach 1:
The receiver architecture performs preliminary signal conditioning by transforming the differential DQS input signal through multiple linear receiver stages with programmable voltage swings and delays before the actual sampling occurs. This preliminary action ensures that the signals are properly aligned and stabilized, creating a reliable sampling window even at high operating speeds where the transition window is narrow.
Solution Approach 2:
The programming architecture enables the receiver stages to be configured based on feedback about signal conditions and timing relationships. By adjusting the voltage swings and delays in response to measured skew conditions, the system maintains accurate sampling at high data transfer rates while minimizing the risk of sampling during transitions.
3Manufacturing precision
If multiple receiver stages are added to reduce skew, then signal alignment improves, but device complexity increases
Solution Approach 1:
Each linear receiver stage is designed with multi-functionality, incorporating both voltage swing transformation and delay adjustment capabilities within the same structural framework. This universal design allows the stages to perform multiple functions (signal transformation, alignment, and conditioning) simultaneously, reducing the need for separate dedicated circuits and thereby limiting the increase in overall device complexity while achieving precise signal alignment.
Data Source
AI summary
Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has a first programmable swing voltage associated therewith. The second stage has a programmable shift voltage associated therewith, and the third stage has a second programmable swing voltage associated therewith. The receiver architecture also includes a programming architecture coupled to the first stage, the second stage, and the third stage. The programming architecture is configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage.