Adaptive Buffer Circuit for Memory Row-Column Failure Repair
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Solution Overview
Problem
Conventional high-capacity memory modules experience significant permanent failures at the memory device level, necessitating entire module replacement due to impracticality of replacing individual devices, which impacts performance and capacity.
Innovation Solution
A buffer circuit with adaptive repair capability, utilizing match circuits to identify and redirect data from defective storage locations to repair resources, minimizing wholesale replacements by isolating memory devices from the primary bus and employing memory repair logic to adaptively repair failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If increasing numbers of memory devices are employed on high-capacity memory modules, then storage capacity is improved, but cumulative yield problems worsen leading to permanent failures
Solution Approach 1:
The patent implements preliminary action by pre-configuring repair logic and substitute storage locations before failures occur. The buffer circuit is designed with built-in repair capabilities that can automatically detect and redirect data from defective locations, preventing complete module failure even when memory devices fail during operation.
Solution Approach 2:
The patent applies parameter changes by dynamically altering the operational state of memory addresses. When a failure is detected, the system changes the status of affected addresses from active to repaired, and redirects data flow to substitute locations. This allows the memory module to adapt its parameter configuration in response to failures while maintaining overall functionality.
2Reliability
If individual memory devices are replaced after failure, then reliability is improved, but the impracticality of replacement worsens leading to entire module replacement
Solution Approach 1:
The patent implements self-service through automatic failure detection and repair mechanisms within the buffer circuit. The repair logic continuously monitors memory device status and autonomously redirects data from failed locations to substitute storage, eliminating the need for manual intervention or physical device replacement by technicians.
Solution Approach 2:
The patent uses an intermediary approach by introducing a buffer circuit with repair logic as a mediator between the memory devices and the system. This intermediary layer handles failure management, absorbing the impact of device failures and maintaining system operation without requiring direct intervention at the device level.
3Reliability
If entire memory modules are replaced due to failures, then reliability is improved, but system performance and capacity are worsened due to loss of operational memory
Solution Approach 1:
The patent applies segmentation by dividing the memory module into independently manageable segments. When a failure occurs in one memory device, only that specific device and its corresponding substitute location are affected, while the rest of the module continues to operate normally. This localized approach preserves overall system performance and capacity.
Solution Approach 2:
The patent implements beforehand cushioning by pre-allocating substitute storage locations and repair resources within the buffer circuit. These cushioning resources are prepared in advance to absorb and compensate for potential failures, ensuring that system performance is maintained without requiring complete module replacement.
4Measurement precision
If match circuits are used to identify defective locations, then repair precision is improved, but device complexity worsens due to additional circuitry
Solution Approach 1:
The patent applies universality by designing the buffer circuit to perform multiple functions: normal data buffering, failure detection, address matching, and data redirection. This multi-functional approach consolidates what could be separate complex circuits into a single integrated buffer structure, managing complexity while maintaining precision.
Data Source
AI summary
A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.