Digital Storage TRIZ Cases

A feedback circuit compares sensed and reference current to adjust negative word-line bias, limiting DRAM leakage and stabilizing refresh.

Segmented ferromagnetic layers with perpendicular anisotropy raise MR ratio and domain-wall controllability for stable multi-state memory.

A segmented SOT electrode writes true and complementary bits together, improving MRAM differential read reliability without extra write energy.

Higher-amplitude recovery pulses repair porous-area damage in resistive memory cells, extending write lifetime while preserving normal writes.

Localized low- and high-concentration doping in stacked memory channel patterns raises 3D integration while avoiding finer planar patterning.

Feedback-controlled pump triggering refreshes adjacent victim rows to limit row hammer data loss while avoiding unnecessary DRAM power use.

Backside metallization routes signals and supply lines to SRAM tracking cells, preserving nominal cell behavior while improving timing accuracy.

Selective voltage shutdown in a slave DRAM chip cuts power use while preserving multi-category DRAM support through master control.

Periodic auto-refresh during DRAM initialization stabilizes cell charge and bit line voltage for faster sensing with lower power and fewer failures.

Injected current pulses speed low-to-high resistive-state reads, enabling single-cycle sensing for high-resistance memory bit cells.

Independent read and read/write bus groups let one memory adapt to different data access ratios and bandwidth needs in network devices.

A narrow SiGe channel on a wider substrate cuts GIDL leakage while enabling off, semi-conducting, and full-conducting transistor states.

Using both rising and falling clock edges, this memory command scheme cuts pre-charge delay and improves continuous access throughput.

Socketed sub-block layouts couple access lines to decoders in multi-deck cross-point memory, reducing routing complexity, cost, and yield loss.

Selection transistors decouple SRAM pull-up paths during writes, improving write capacity and read stability without larger transistors.

Field-programmable ferroelectric diodes enable transistor-free storage, TCAM search, and neural computing with low data movement and high energy efficiency.

A vertical double-gate stack cuts leakage in dense storage arrays while preserving on-current and reducing occupied area.

A shared bit-line pad with connected first and second bit lines reduces layout area and supports higher cell density with solid electrical performance.

Partition offsets spread logical column data across memory partitions, cutting column-read media management delays in 3D cross-point memory.

Write-pointer buffering across long interconnects avoids retimed flip-flops, simplifying clock trees and reducing chip area and power.

A wider-top MTJ stack with sidewall spacers limits metal re-sputtering during etch, reducing shorts and improving MRAM scalability.

Quantized timing parameters and a correction factor cut memory clock-cycle computation latency while preserving access timing accuracy.

Controller logic maps a faulty row to a spare row while other memory banks keep running, reducing sPPR latency and preserving data.

Embedded AMMC enables local processing in resistive memory, cutting off-chip access power and latency while extending battery life.

Temperature-driven back-gate bias stabilizes threshold voltage, balancing on-state current, speed, data retention, and low power.

An oxide-surrounded self-aligned MTJ bottom electrode prevents metal re-sputtering, reducing shorts and preserving layer integrity in MRAM.

Vertical multi-transistor bitcell stacks share source-drains to shorten bitlines, cut capacitance, and raise ROM density.

Split channel layers with different resistance cut SOT-MRAM write power while preserving read current, TMR ratio, and read speed.

Shared-material bit line capping and boundary patterns reinforce narrow bit lines, preventing defects and preserving structural integrity at high density.

An inverted T-shaped bottom electrode concentrates the electric field to speed filament formation and RRAM state switching.

LFU-based row tracking uses primary and auxiliary records to refresh frequently accessed DDR rows and reduce adjacent-row bit flips.

Opposite-side quad-channel DRAM routing doubles memory capacity while limiting signal loading and preserving high data rates in dual-channel mode.

A timing delay circuit and shadow latch let SRAM DFT mode match normal output hold time, improving valid read windows and test reliability.

Fly-bitlines enable single-ended SRAM sensing to cut sense-amplifier complexity, chip area, and power without slowing memory access.

Different top and bottom electrode contact areas widen the sensing window in self-selecting memory cells, improving read accuracy and reducing refresh power.

Multilayer SAF regions raise the MTJ energy barrier at smaller MRAM nodes while lowering critical current to protect write and reset reliability.

Match circuits compare row and column addresses to redirect data around failed memory locations without replacing the whole module.

Distance-based current control compensates memory-line resistance, enabling reliable writes to near and far cells without half-biasing.

Redundant row access counts and majority-vote correction improve aggressor row detection despite memory-cell errors such as neutron strikes.

Selective P-type work function metal removal in SRAM transistors offsets layout-driven fin current mismatch and improves cell stability.

Selective bit-line and plate-line voltages keep unselected ferroelectric cells below switching thresholds, widening read window and cutting refresh frequency.

Alternating recovery pulses restore the FeFET ferroelectric-oxide interface after program and erase stress, improving write endurance and bit error rates.

A heat dispersion layer cools the bottom electrode interface in PMCs, stabilizing conductive bridge formation and set/reset voltages.