Fly-Bitline SRAM Readout With Single-Ended Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional single-port SRAM bit-cells require complex pre-charging timing control and differential sense amplifiers with high gate count, leading to large chip area and high power consumption.
Innovation Solution
Implementing a memory design with fly-bitlines that utilize single-ended sensing and a single-ended sense amplifier circuit, which includes a logic gate and an output latch, eliminating the need for differential sensing and reducing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If differential sense amplifier is used for reading SRAM bit-cell, then measurement precision is improved, but device complexity increases and power consumption increases
Solution Approach 1:
The patent extracts the differential sensing function and replaces it with single-ended sensing. Instead of using a complex differential sense amplifier that requires two bitlines (BL and BLB), the invention uses a simple single-ended sense amplifier that only requires one bitline (BL), thereby reducing device complexity while maintaining reading capability through the fly-bitline mechanism
Solution Approach 2:
The fly-bitline (BLF) serves multiple functions: it acts as a virtual extension of the physical bitline to reduce RC delay, functions as a charging path during read operations, and enables single-ended sensing to work effectively. This multi-functional design allows the system to achieve differential-like performance with single-ended hardware
2Measurement precision
If differential sense amplifier is used for reading SRAM bit-cell, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming differential sense amplifier and replaces it with a low-power single-ended sense amplifier. The fly-bitline mechanism enables this simplification by providing virtual bitline extension that maintains signal integrity without requiring the complex differential amplification circuitry that consumes significant power
Solution Approach 2:
The invention uses simple, low-cost single-ended sensing circuitry instead of expensive differential sense amplifiers. The fly-bitline acts as a temporary virtual extension that exists only during the read operation, enabling simple circuitry to achieve the performance of complex circuitry at lower power cost
3Ease of operation
If pre-charging timing control and pass-gate timing control are implemented, then reading operation is improved, but device complexity increases
Solution Approach 1:
The patent removes the complex pre-charging timing control and pass-gate timing control mechanisms from traditional differential sensing. The fly-bitline-based single-ended sensing inherently simplifies the read operation by using the fly-bitline as a natural charging path, eliminating the need for complex timing control circuits while maintaining proper read operation sequencing
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory includes a memory array and a single-ended sense amplifier circuit. The memory array includes wordlines, bitlines, and memory cells. The bitlines include a first bitline, routed on a first metal layer but not a second metal layer, and a second bitline, routed on the first metal layer and the second metal layer. Each of the memory cells is coupled to one of the wordlines. The memory cells include a first group of memory cells, coupled to the first bitline, and a second group of memory cells, coupled to the second bitline, where the first group of memory cells and the second group of memory cells are located at a same column. The single-ended sense amplifier circuit performs a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled.