Single-Ended Sense Amplifier With Current Pulse Read Acceleration
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Solution Overview
Problem
Existing single ended sense amplifiers in memory devices like RRAM and MRAM require two clock cycles for read operations due to slower processing times during low to high data transitions, particularly when dealing with high bit cell resistances, leading to latency issues.
Innovation Solution
A parallel current path and masking technique are introduced in the sense amplifier to facilitate a single clock cycle read operation by injecting additional current during low to high transitions using a pulse generation circuit, while avoiding current injection during high to low transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single ended sense amplifier is used for reading data from bit cells, then the circuit structure remains simple, but the read operation requires two clock cycles due to slower processing during low to high transitions
Solution Approach 1:
The patent applies dynamics by making the current path configurable between series and parallel configurations based on the data transition type. The sense amplifier dynamically adjusts its operating mode: using series connection for high to low transitions and parallel connection for low to high transitions, thereby optimizing read speed for each case while maintaining circuit simplicity through controlled reconfiguration
Solution Approach 2:
The patent changes the electrical parameters of the sense amplifier by switching between different resistance configurations. The bit line resistance is dynamically adjusted by changing from series to parallel connection of the first and second bit line resistors, allowing optimization of the read operation characteristics for different data transition scenarios
2Loss of time
If additional current is injected during low to high transitions to speed up charging, then the read operation completes in single clock cycle, but the circuit complexity increases with pulse generation circuit
Solution Approach 1:
The sense amplifier circuit performs self-service by using its own internal components (first and second bit line resistors) to generate the current injection effect. The parallel connection configuration inherently provides the additional current path needed for low to high transitions, eliminating the need for external pulse generation circuits while maintaining the speed improvement
Solution Approach 2:
The first and second bit line resistors serve multiple functions: they act as regular resistive elements during normal operation and simultaneously function as current injection sources when connected in parallel during low to high transitions. This multi-functionality reduces the need for additional dedicated components
Data Source
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AI summary
Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.