Register File Voltage Boosting via Distributed Capacitor Blocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory devices face limitations in voltage boosting techniques for register files, particularly in large configurations, which are not compiler-friendly and fail to effectively adjust for different memory sizes and configurations, leading to excessive boost and area penalties.
Innovation Solution
The introduction of a dummy word-line row and strategically placed circuit blocks, including flying capacitor circuits and isolation devices, to detect and adjust voltage boost timing and capacitance, allowing for scalable voltage boosting that minimizes area penalty and reduces leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional voltage boosting techniques are used in large register file configurations, then voltage boost is achieved, but area penalty and leakage current increase excessively
Solution Approach 1:
The register file is divided into multiple banks, and voltage boosting is applied selectively to specific banks rather than the entire register file. This segmentation allows voltage boost to be applied only where needed, reducing the overall area penalty and leakage current while maintaining the necessary voltage boost for proper operation.
Solution Approach 2:
Different voltage boosting strategies are applied to different regions of the register file based on local requirements. The patent implements region-specific voltage control where only certain banks or regions receive voltage boosting, optimizing the balance between achieving necessary voltage levels and minimizing area penalty and leakage.
2Power
If conventional voltage boosting techniques are used, then voltage boost is achieved, but the solution is not compiler-friendly and fails to adjust for different memory configurations
Solution Approach 1:
The voltage boosting mechanism is made dynamic and configurable, allowing it to adapt to different register file sizes, bank configurations, and memory layouts. The patent implements configurable control logic that can be programmed or compiled to match specific memory configurations, making the solution compiler-friendly and adaptable to various scenarios.
Solution Approach 2:
The patent changes key parameters such as the number of boosted banks, the duration of voltage boosting, and the threshold for triggering voltage boost based on the specific memory configuration. These parameter adjustments allow the same hardware structure to adapt to different register file sizes and configurations without excessive area penalty.
3Reliability
If voltage boosting is applied to ensure proper operation, then minimum operating voltage is maintained, but excessive boost increases area and leakage
Solution Approach 1:
The patent implements feedback mechanisms that monitor the actual voltage levels and operational needs of different register file banks. Based on this feedback, the voltage boosting is adjusted dynamically - applying boost only when and where it is actually needed to maintain minimum operating voltage, thereby avoiding excessive boost that would increase leakage current and area penalty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables area-efficient and compiler-friendly voltage boosting, reducing the minimum operating voltage and memory area, while preventing excessive boost, and is applicable to various memory configurations such as segmented-write and bit-write.
Implementation Method 1
a capacitor having a first plate coupled to a second node
Data Source
AI summary
Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second node and to decouple the first node from the second node, circuit blocks coupled to the second node and the switching circuit, and drivers coupled to the second node. Each of the circuit blocks includes a capacitor having a plate coupled to the second node. Each of the drivers is associated with a conductive line. The conductive line is associated with memory cells.