MRAM Write Circuit Data Comparison Control

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Solution Overview

Problem

Existing magnetoresistive random access memory (MRAM) technologies face challenges in reducing write current and power consumption, especially as device size decreases, leading to potential memory cell deterioration and increased power consumption during write operations, particularly when interruptions occur during write commands.

Innovation Solution

The proposed MRAM design incorporates a controller that manages write operations by entering a wait state and performing sequential transfer operations, ensuring that data is correctly written to memory cells without unnecessary write currents, thereby reducing power consumption and minimizing memory cell deterioration. This is achieved through a column control circuit that compares data before writing and uses a write enable control circuit to manage write enable signals, ensuring that write operations are completed without interruptions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If write operations are performed frequently to update data in memory cells, then data accuracy is maintained, but power consumption increases and memory cell deterioration occurs

Engineering Contradiction:
Improvedata accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by performing data comparison before write operations. The controller compares new data with existing data in the memory cell before initiating a write operation. When the data is determined to be unchanged, the write operation is skipped, thereby avoiding unnecessary write currents and reducing power consumption while maintaining data accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the data comparison mechanism. The controller continuously monitors the data state in memory cells and uses this feedback to determine whether a write operation is necessary. This feedback loop prevents redundant write operations, reducing the total number of write currents applied to memory cells and consequently lowering power consumption.

Inventive Principle:
Principle #23Feedback

2Reliability

If write operations are performed frequently to update data in memory cells, then data accuracy is maintained, but memory cell deterioration increases

Engineering Contradiction:
Improvedata accuracyVSAvoidmemory cell durability
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent applies preliminary action by performing data comparison before write operations. The controller compares new data with existing data in the memory cell before initiating a write operation. When the data is determined to be unchanged, the write operation is skipped, thereby avoiding unnecessary write currents and reducing power consumption while maintaining data accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the data comparison mechanism. The controller continuously monitors the data state in memory cells and uses this feedback to determine whether a write operation is necessary. This feedback loop prevents redundant write operations, reducing the total number of write currents applied to memory cells and consequently lowering power consumption.

Inventive Principle:
Principle #23Feedback

3Loss of time

If write operations are interrupted during write commands, then response time is reduced, but data integrity may be compromised

Engineering Contradiction:
Improveresponse timeVSAvoiddata integrity
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent applies preliminary action by performing data comparison before write operations. The controller compares new data with existing data in the memory cell before initiating a write operation. When the data is determined to be unchanged, the write operation is skipped, thereby avoiding unnecessary write currents and reducing power consumption while maintaining data accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the data comparison mechanism. The controller continuously monitors the data state in memory cells and uses this feedback to determine whether a write operation is necessary. This feedback loop prevents redundant write operations, reducing the total number of write currents applied to memory cells and consequently lowering power consumption.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the number of write operations, minimizes power consumption, and prevents memory cell deterioration by ensuring that write operations are completed without interruptions, thereby enhancing the durability and efficiency of the MRAM.

Implementation Method 1

MRAMs are memory devices using magnetoresistive elements having a magnetoresistive effect as memory cells storing information

Methodology Applied
Scientific EffectMagnetoresistive effect: Magnetoresistance

Implementation Method 2

Writing methods of MRAMs include a spin-transfer torque writing method. The spin-transfer torque writing method has a property that a spin-transfer torque current necessary for magnetization switching reduces as the size of the magnetic substance reduces

Methodology Applied
Scientific EffectSpin-transfer torque:

Data Source

PatentUS9966124B2Memory device
Publication Date: 2018.05.08 KIOXIA CORP

AI summary

A memory device includes: a memory cell; a data buffer which receives write data; a first latch circuit which latches data stored in the memory cell; a second latch circuit which latches data transferred from the data buffer; a controller which performs a first transfer operation to transfer data from the data buffer to the second latch circuit after a write command is received and then a first period elapses; and a write circuit which performs a write operation to write data of the second latch circuit to the memory cell after the first transfer operation, when data of the first latch circuit is different from the data of the second latch circuit. The controller performs a second transfer operation to transfer data from the second latch circuit to the first latch circuit after the write operation.