SRAM Read Cell Work Function Tuning for Current Balance
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Solution Overview
Problem
The current static random access memory (SRAM) experiences current imbalance due to differences in passing currents of pull-down and access transistors, caused by variations in fin structure span lengths, leading to performance issues.
Innovation Solution
Adjust the P type work function metal layer of certain N type transistors to balance the saturation current, specifically by reducing or partially removing the P type work function metal layer in selected transistors to enhance current balance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the fin structure span lengths are varied due to layout pattern, then the transistor passing currents differ, but this leads to current imbalance in the SRAM
Solution Approach 1:
The patent applies local quality by selectively removing the P type work function metal layer from specific N type transistors (first pull-down transistor and second access transistor) while retaining it in others. This creates localized differences in work function and saturation current, allowing current balance to be achieved in specific regions of the circuit without affecting the entire layout. The selective modification enables the SRAM to maintain current balance despite variations in fin structure span lengths caused by layout patterns.
2Reliability
If the P type work function metal layer is reduced in selected N type transistors, then the saturation current of these transistors increases, but this requires precise manufacturing control
Solution Approach 1:
The patent segments the work function metal layer structure by selectively removing the P type layer from only certain transistors (first pull-down and second access transistors) while leaving it intact in others. This segmentation is achieved through selective masking and etching processes that target specific transistor regions. The segmentation approach allows precise control over which transistors receive the work function modification, enabling current balance adjustment without requiring uniform modification across all devices.
Solution Approach 2:
The patent changes the work function parameter of specific transistors by selectively removing the P type work function metal layer. This parameter change directly affects the saturation current of the modified transistors, increasing it to compensate for current imbalance. The selective removal process allows precise control over the work function parameter in specific devices, enabling fine-tuning of current characteristics to achieve overall circuit balance.
3Ease of manufacture
If the fin structure span is cut off due to layout pattern, then manufacturing is simplified, but this causes difference in passing currents of transistors
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for the current imbalance that would result from layout-induced fin structure variations. Before finalizing the transistor characteristics, the P type work function metal layer is selectively removed from specific transistors to counterbalance the expected current differences caused by the layout pattern. This preliminary adjustment ensures that even though the fin structures have different span lengths, the overall current matching in the SRAM circuit is maintained.
Data Source
AI summary
The invention provides a static random access memory, which includes at least a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPD). Wherein the gate structures of the first pull-down transistor (PD1) and the second access transistor (PG2) each include a P type work function metal layer, and an N type work function metal layer is located on the P type work function metal layer in the gates of the first pull-down transistor (PD1) and the second access transistor (PG2).