Sub Word Line Driver Activation for Semiconductor Memory Testing
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Solution Overview
Problem
Current semiconductor memory apparatuses face challenges in effectively detecting defective elements during wafer burn-in tests, as existing methods may not adequately identify leakage currents between sub word line drivers and defective elements.
Innovation Solution
A semiconductor memory apparatus is designed with a decoding unit that enables specific sub word line driver enable signals in both normal and test modes, allowing for the arrangement of inactivated sub word line drivers between activated ones to detect leakage currents and identify defective elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all sub word line drivers are activated during testing, then complete coverage of defect detection is achieved, but testing time increases and leakage current detection becomes difficult
Solution Approach 1:
The patent divides the sub word line drivers into multiple groups (first sub word line driver group and second sub word line driver group) and activates them in alternating sequences during different test periods. This segmentation allows systematic testing of all drivers while controlling testing time and enabling leakage current detection by comparing activated and inactivated drivers.
Solution Approach 2:
The patent implements periodic activation patterns where sub word line drivers are activated and deactivated in alternating sequences across different test periods. During first test period, first group is activated while second group is inactivated, and vice versa during second test period. This periodic action enables leakage current detection and complete defect coverage without requiring all drivers to be activated simultaneously.
2Measurement precision
If sub word line drivers are arranged in a simple sequence, then device complexity is reduced, but leakage current detection capability is compromised
Solution Approach 1:
The patent arranges sub word line drivers in a specific local pattern where inactivated drivers are positioned between activated drivers within each group. This local arrangement creates measurable voltage differences that enable leakage current detection while maintaining a relatively simple overall driver structure and control mechanism.
Data Source
AI summary
A semiconductor memory apparatus may include a decoding unit configured to enable one of a plurality of sub word line driver enable signals by decoding a plurality of addresses while the decoding unit operates in a normal mode, and enables specific sub word line driver enable signals among the plurality of sub word line driver enable signals regardless of the plurality of addresses while the decoding unit is operating in a test mode. The semiconductor memory apparatus may include a sub word line driver group configured to include a plurality of sub word line drivers, the plurality of sub word line drivers configured for activation in response to the plurality of sub word line driver enable signals. The sub word line driver group is configured so that inactivated sub word line drivers are arranged between activated sub word line drivers while the decoding unit is operating in the test mode.