SRAM DFT Shadow Latch for Equal Output Hold Timing
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Solution Overview
Problem
Existing SRAM circuits face challenges in maintaining similar output hold times during design-for-test (DFT) mode and normal operation, leading to output hold degradation due to narrow time windows for valid data reading.
Innovation Solution
Implementing a timing path through the SRAM circuit that mimics normal operation, using a timing delay circuit and multiplexer to ensure equal output hold times in both modes by enabling a shadow latch and sense amplifier during DFT mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DFT circuit is implemented in SRAM to enable testing functionality, then testability and fault detection capability are improved, but output hold time degrades due to narrow time windows for valid data reading
Solution Approach 1:
The patent segments the output path into two separate paths: a normal operation path and a DFT test path. The normal read path maintains standard output hold time characteristics, while the DFT path uses a dedicated test read circuit with extended hold time capability. This segmentation allows each path to be optimized independently for its specific function without compromising the other.
Solution Approach 2:
The patent introduces an intermediary test read circuit that acts as a mediator between the SRAM array and the test equipment. This intermediate circuit includes additional latching elements and control logic that extend the output hold time specifically for DFT operations, while leaving the normal read path unchanged. The intermediary buffer absorbs the timing differences between the two modes.
2Reliability
If additional DFT circuitry is added to the SRAM, then testing reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the DFT test read circuit functionality with the existing SRAM read circuit architecture. The test read circuit shares common elements with the normal read path, such as word line decoding and bit line sensing, while adding only the necessary additional latching and control logic specifically for extending output hold time. This merging approach minimizes the increase in device complexity.
Solution Approach 2:
The patent designs the test read circuit with multi-functionality, where the same circuit structure serves both normal read operations and DFT test operations. The circuit can dynamically switch between modes based on control signals, making the additional circuitry serve dual purposes rather than being dedicated solely to testing, thereby reducing the net increase in complexity.
Data Source
AI summary
A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a memory circuit configured to receive a clock signal and generate an output signal. The memory circuit includes a timing delay circuit. The semiconductor device includes a design-for-test (DFT) circuit comprising a shadow latch. The DFT circuit is configured to receive an output of the timing delay circuit, and generate a DFT output signal via the shadow latch. A first output hold of the output signal is about equal to a second output hold of the DFT output signal.