Memory Controller Row Mapping for Parallel Bank Repair
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Solution Overview
Problem
Traditional Soft Post Package Repair (sPPR) processes in memory devices are complex and result in increased latency and data loss due to the need to stop read/write commands to all banks during the repair process, without effectively retaining data before mapping to spare rows.
Innovation Solution
Implementing logic in the memory controller that is connected to the scheduler and refresh circuitry to allow parallel execution of sPPR with other commands, while retaining data by moving it to spare rows, thus preventing data loss and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sPPR process stops scheduler from issuing commands to all banks during repair, then row mapping to spare row can be performed, but latency increases and productivity decreases
Solution Approach 1:
The memory system is divided into multiple independent banks, allowing the repair operation on one bank to proceed independently while other banks continue normal operations. The scheduler is segmented to handle bank-specific commands separately, enabling parallel processing of repair and data operations across different banks.
Solution Approach 2:
The useful action of data access continues uninterrupted in non-affected banks while the repair operation proceeds in the target bank. The scheduler maintains continuous operation by issuing commands to healthy banks simultaneously with the repair process, eliminating idle time and maintaining overall system productivity.
2Reliability
If traditional sPPR process stops all read/write commands during mapping, then data integrity can be maintained during repair, but latency increases
Solution Approach 1:
The repair operation applies local quality control only to the specific bank undergoing repair, while other banks maintain their normal data access patterns. This localized approach ensures data integrity in the repair zone without imposing restrictions on the rest of the system, thereby reducing overall latency.
Solution Approach 2:
The system performs preliminary data validation and scheduling adjustments before the actual mapping operation begins. The scheduler prepares command queues in advance to ensure seamless continuation of operations in non-affected banks, minimizing disruption and latency during the repair process.
3Device complexity
If traditional sPPR process is implemented without parallel command execution, then mapping complexity is reduced, but device complexity increases due to sequential processing requirements
Solution Approach 1:
The scheduler dynamically adapts its command issuance based on the repair status of each bank. It automatically adjusts command routing to exclude banks undergoing repair while maintaining full operational capacity in healthy banks, enabling flexible parallel processing without increasing overall system complexity.
Solution Approach 2:
The scheduler performs multiple functions simultaneously: it manages normal data access commands for healthy banks, coordinates repair operations for affected banks, and dynamically reallocates resources as needed. This multi-functionality maintains mapping process simplicity while significantly improving command processing efficiency.
Data Source
AI summary
A row can be mapped to a spare row in memory. The mapping can include stopping the scheduler from issuing commands to the first bank. Responsive to stopping the scheduler from issuing commands to the first bank, the logic can map a particular row of the first bank to the spare row. The mapping can include allowing the scheduler to schedule commands for the second bank concurrently with the mapping of the particular row to the spare row.