SOT-MRAM Channel Layer Segmentation for Low-Power Fast Readout
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Solution Overview
Problem
Existing three-terminal SOT-MRAMs face challenges with high power consumption due to large write currents in the channel layer, which increases load resistance and reduces the TMR ratio, leading to slower reading speeds, especially in integrated circuits.
Innovation Solution
The magnetoresistive effect element incorporates a first channel layer with higher resistance than a second channel layer, allowing for adjusted overall resistance values to manage power consumption while maintaining a large read current for high-speed reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the resistance of the channel layer is increased to reduce write current, then power consumption decreases, but the read current becomes smaller and reading speed slows down
Solution Approach 1:
The channel layer is divided into two separate channel layers with different resistance values. The first channel layer has higher resistance to reduce write current and power consumption, while the second channel layer has lower resistance to maintain large read current for high-speed reading. This segmentation allows independent optimization of write and read operations.
Solution Approach 2:
Different regions of the channel structure are assigned different resistance characteristics. The first channel layer region is designed with high resistance for write operations, while the second channel layer region is designed with low resistance for read operations. This local differentiation resolves the contradiction between power consumption and reading speed.
2Loss of energy
If the resistance value of the channel layer is made larger, then write current decreases and power consumption is reduced, but the TMR ratio decreases and reading becomes slower
Solution Approach 1:
The channel layer is segmented into two distinct layers with different resistance values optimized for different operations. The first channel layer's higher resistance reduces power consumption during writing, while the second channel layer's lower resistance ensures fast reading by maintaining large read current and high TMR ratio.
Solution Approach 2:
The system dynamically switches between different channel layer configurations depending on the operation mode. During write operations, the higher resistance first channel layer is utilized to reduce power consumption. During read operations, the lower resistance second channel layer is utilized to minimize reading time and maintain high TMR ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables low power consumption and high-speed writing and reading by optimizing the resistance values of the channel layers, enhancing the TMR ratio and reducing read time.
Implementation Method 1
The channel layer 1111 is a conductive layer made of a heavy metal or the like, and a region where the spin orbit torque is generated when the write current flows.
Implementation Method 2
When the direction of magnetization M1112 of the recording layer 1112 is the same as the direction of magnetization M1114 of the reference layer 1114 (parallel state), resistance between the reference layer 1114 and the recording layer 1112 decreases. On the other hand, when the direction of magnetization M1112 of the recording layer 1112 is opposite to the direction of magnetization M1114 of the reference layer 1114 (antiparallel state), resistance between the reference layer 1114 and the recording layer 1112 becomes relatively large.
Data Source
AI summary
A magnetoresistive effect element includes a reference layer, a barrier layer, a recording layer, and a channel layer that are disposed on top of one another, and a first terminal connected to the reference layer, and a second terminal and a third terminal connected to the channel layer. The channel layer includes a first channel layer and a second channel layer, the first channel layer has electrical resistance larger than electrical resistance of the second channel layer, the second terminal is connected to the first channel layer, and the third terminal is connected to the second channel layer, a write current flows between the second terminal and the third terminal via the first channel layer and the second channel layer, and a read current flows between the first terminal and the third terminal.