Register File Arrays Multiplexed Read Path Leakage Reduction
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Solution Overview
Problem
Current register file (RF) memory bitcells with large read ports and low threshold voltage transistors achieve fast read speed but result in high leakage current during idle conditions, and existing techniques to improve area efficiency either sacrifice read performance or increase power consumption.
Innovation Solution
The implementation of a multiplexer with n-type metal-oxide-semiconductor (NMOS) column multiplexer transistors and a flying bitline technique that precharges local bitlines to a lower voltage, allowing multiple bitcells to share read merge circuitry, reducing leakage current and improving area and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large read ports and low threshold voltage transistors are used in register file bitcells, then read speed is improved, but leakage current increases during idle conditions
Solution Approach 1:
The register file is divided into multiple banks, each with its own dedicated read merge circuitry. This segmentation allows independent control of each bank's read ports, enabling the circuit to use large read ports for fast access when needed while allowing idle banks to enter low-power states with reduced leakage current.
Solution Approach 2:
The patent implements dynamic control of read merge circuitry that can be selectively enabled or disabled based on access patterns. When a bank is not being accessed, its read merge circuitry can be deactivated, dynamically reducing leakage current while maintaining fast read capability when access is required.
2Productivity
If cache capacity is increased to improve single-threaded performance, then performance is improved, but leakage current percentage increases
Solution Approach 1:
The large cache is organized into multiple smaller banks rather than a single large array. Each bank can be independently accessed and independently powered down, allowing the system to maintain large total capacity for improved performance while reducing overall leakage by keeping only actively accessed banks in high-power states.
Solution Approach 2:
Each bank shares common control logic and read merge circuitry that can serve multiple functions. The read merge unit can handle reads from any bank, and the same control mechanisms manage both performance-critical access paths and power-management functions across all banks.
3Area of stationary object
If more bits per bitline are implemented to achieve area efficiency, then area efficiency is improved, but read performance and minimum operating voltage deteriorate
Solution Approach 1:
Instead of creating long bitlines that combine many bits, the patent segments the bitline structure into shorter local bitlines within each bank. This segmentation maintains area efficiency through compact bank organization while preserving read performance by limiting bitline length and capacitance, ensuring fast signal propagation and maintaining minimum operating voltage requirements.
Data Source
AI summary
Various embodiments provide apparatuses, systems, and methods for a register file array with a plurality of sets of memory cells, wherein individual sets of memory cells of the plurality of sets of memory cells are coupled to a respective local bit line (LBL). A merge circuitry may include a multiplexer with inputs coupled to the respective LBLs, wherein the multiplexer is to couple a selected one of the LBLs to a LBL merge node. Read circuitry may be coupled to the LBL merge node to read data from a first memory cell via the selected LBL. In some embodiments, the LBL may be precharged to a supply voltage (e.g., Vcc) minus a threshold voltage, Vt, of the multiplexer transistor, as opposed to being precharged to Vcc as in prior techniques. Other embodiments may be described and claimed.