Data Sorting Control Circuit for Memory Devices
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Solution Overview
Problem
Memory devices face challenges in reducing current consumption while maintaining high data transfer rates, as they sort and output data efficiently in response to increasing operation speeds and varying burst orders determined by seed addresses and clock phases.
Innovation Solution
A memory device with a data sorting control circuit that includes a phase detector, order determiner, and sorting control signal generator to determine data order based on clock signals and seed addresses, generating selection and sorting control signals to serially output data, thereby minimizing changes in burst order and reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data sorting is performed using traditional circuits with multiple control signals, then data transfer rate is improved, but current consumption increases
Solution Approach 1:
The patent combines multiple sorting control signals into a single sorting control signal that determines the burst order of read data. This merging of control functions reduces the number of signals required and consequently lowers current consumption while maintaining the data sorting capability needed for high transfer rates
Solution Approach 2:
The sorting control circuit is designed to handle multiple sorting scenarios (different burst orders) using a universal control mechanism. The single sorting control signal can configure different data orders (first order or second order) based on clock phase detection, providing multi-functionality without requiring separate control circuits for each sorting mode
2Adaptability or versatility
If multiple sorting control signals are used to handle varying burst orders, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic adaptability by detecting the phase of clock signals and automatically adjusting the data order accordingly. The sorting control circuit dynamically switches between first order and second order data sorting based on the detected clock phase, providing adaptability without requiring manual configuration or complex static control logic
Solution Approach 2:
The sorting control circuit automatically determines the appropriate data order by detecting clock phases and generating the corresponding sorting control signal without external intervention. The system self-configures the burst order based on internal clock signal characteristics, reducing the need for external control signals and simplifying the overall control architecture
Data Source
AI summary
A data sorting control circuit includes a phase detector suitable for detecting a phase of each of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in response to a read command, an order determiner suitable for determining a data order as a first order or a second order based on a seed address and the detected phase of each of the clock signals, and an sorting control signal generator suitable for shifting the read command based on the first clock signal to the fourth clock signal to generate a first sorting control signal, a second sorting control signal, a third sorting control signal, and a fourth sorting control signal, and outputting the first sorting control signal to the fourth sorting control signal according to the first order or the second order.