Nullifying DFE Tap Contributions at Memory Clock Restart
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional techniques fail to effectively nullify incorrect sampled data contributions in a decision feedback equalizer (DFE) during the restart of a forwarded clock in memory systems, leading to reduced margin due to error propagation and stale past history.
Innovation Solution
A method and apparatus that include a receiver circuit with a data buffer configured to initialize conditions and generate tap enable signals to delay contributions of DFE taps, synchronize tap load control signals with a forwarded source-synchronous pin clock, and prevent tap contributions until known good data is registered, thereby improving DFE margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional techniques are used to sample data in DFE during clock restart, then the system operates continuously, but incorrect sampled data contributions propagate causing margin reduction
Solution Approach 1:
The patent applies preliminary action by detecting the clock restart condition before incorrect data sampling occurs and proactively nullifying the DFE tap contributions. The control logic identifies when the forwarded clock restarts and generates a nullification signal to clear stale data from the DFE memory elements before they can contaminate subsequent equalization decisions, thus maintaining reliability during continuous operation.
Solution Approach 2:
The patent introduces an intermediary control logic circuit that mediates between the clock signal and the DFE tap contributions. This control logic monitors the clock restart condition and generates a nullification control signal that temporarily disables the DFE tap contributions to memory elements, acting as a mediator that prevents incorrect data propagation while allowing normal operation to resume.
2Measurement precision
If DFE tap contributions are continuously updated, then equalization performance is maintained, but stale past history causes error propagation at first data transition bit
Solution Approach 1:
The patent applies the taking out principle by extracting and removing the harmful stale data contributions from the DFE memory elements at the specific moment when clock restart occurs. The nullification control signal selectively clears the tapped-delay elements and memory elements that would otherwise propagate incorrect historical data, separating the useful equalization function from the harmful error propagation.
Solution Approach 2:
The patent applies preliminary anti-action by preemptively nullifying the DFE tap contributions before they can cause error propagation. The control logic detects clock restart and immediately generates a nullification signal that counteracts the potential harmful effect of stale data being sampled and stored in the memory elements, preventing the error propagation before it occurs.
3Device complexity
If tap load control signals are not synchronized with forwarded clock, then circuit complexity is reduced, but DFE margin is reduced due to incorrect sampling
Solution Approach 1:
The patent introduces an intermediary control logic circuit that synchronizes the tap load control signals with the forwarded clock without requiring complex synchronization circuitry. The control logic monitors the clock signal and generates appropriately timed nullification control signals that align with the clock edges, achieving synchronization through intelligent control rather than complex hardware.
Solution Approach 2:
The control logic circuit performs self-service by autonomously detecting the clock restart condition and generating the nullification control signals without external intervention. The circuit monitors its own operating conditions and automatically adjusts the DFE tap contributions accordingly, eliminating the need for external synchronization control.
Data Source
AI summary
An apparatus includes a receiver circuit and a data buffer. The receiver circuit may comprise a decision feedback equalizer (DFE). The data buffer circuit may be configured to initialize a condition of the receiver circuit in response to a control signal prior to reception of a command sequence associated with a directed access to a memory system. The control signal generally indicates detection of a non-consecutive clock associated with a start of the command sequence. The data buffer circuit may generate one or more tap enable signals configured to determine a number of clock cycles during which a contribution of one or more taps of the decision feedback equalizer (DFE) are delayed.