Memory Device Impedance Calibration Code Validation
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Solution Overview
Problem
Semiconductor memory devices face impedance mismatch issues due to increasing operating speeds, leading to signal distortions and loss, as the swing width of signals transmitted and received between the device and external devices decreases, causing a portion of the signal to be reflected back rather than being transmitted to the load.
Innovation Solution
A memory device with an impedance calibration method that generates an impedance calibration code using an external resistor connected to an impedance pad, and a calibration control circuit that compares new calibration codes with specified ranges to prevent updates outside these ranges, ensuring accurate impedance calibration based on temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impedance calibration code is updated freely to improve signal transmission, then signal quality may improve, but abnormal calibration codes can cause signal distortions and loss
Solution Approach 1:
The patent applies preliminary action by pre-defining valid impedance calibration code ranges before actual calibration operations. The calibration control circuit checks whether generated calibration codes fall within these predetermined ranges, preventing abnormal codes from being applied. This proactive validation approach avoids signal distortions and loss by ensuring only valid calibration codes are used, thereby improving signal transmission reliability without requiring complex real-time analysis.
2Loss of energy
If impedance calibration is performed to reduce signal loss, then signal transmission quality improves, but the system requires additional calibration control circuits and validation steps
Solution Approach 1:
The patent implements feedback by creating a closed-loop calibration control system. The calibration control circuit generates impedance calibration codes, validates them against predetermined ranges, and only applies valid codes to the input/output circuit. This feedback mechanism ensures that calibration operations actually reduce signal loss by preventing abnormal codes from being applied, while the structured validation approach keeps the added circuit complexity manageable through systematic rather than ad-hoc control.
3Measurement precision
If calibration code range validation is implemented to prevent abnormal codes, then calibration accuracy improves, but the calibration process requires additional comparison steps
Solution Approach 1:
The patent applies preliminary action by pre-establishing valid impedance calibration code ranges before the calibration process begins. During calibration, the control circuit simply compares generated codes against these predetermined ranges using efficient binary comparison logic. This approach significantly improves calibration code accuracy by filtering out abnormal codes, while minimizing time loss because the validation step is a straightforward numerical comparison rather than a complex iterative process.
Data Source
AI summary
A memory device includes: a memory cell array; an input/output circuit controlling inputting and outputting data stored in the memory cell array; an impedance calibration circuit generating an impedance calibration code based on an external resistor connected to an impedance pad for application to the input/output circuit as an applied impedance calibration code; and a calibration control circuit comparing a new impedance calibration code received from the impedance calibration circuit with a calibration code range for generating a calibration code update flag when the new impedance calibration code is included in the calibration code range. The impedance calibration circuit updates the applied impedance calibration code with the new impedance calibration code when receiving the calibration code update flag.