SRAM Tracking Cells Using Backside Metallization for Timing Accuracy
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Solution Overview
Problem
The integration of timing tracking cells in SRAM devices increases routing density, leading to stray capacitance and decreased performance and power efficiency, as additional lines are coupled with memory cells, causing variations in cell behavior and reduced performance.
Innovation Solution
Utilizing backside metallization layers to provide signals to tracking cells, maintaining a similar layout as non-tracking cells, thereby mirroring their function and reducing the impact on nominal memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing tracking cells are integrated into SRAM devices with additional routing lines, then timing tracking functionality is achieved, but stray capacitance increases and performance deteriorates
Solution Approach 1:
The patent utilizes backside metallization layers to route signals to tracking cells, moving the routing from the frontside plane to the backside dimension. This spatial separation reduces stray capacitance and interference with nominal memory cells while maintaining timing tracking accuracy through the third-dimensional metallization path.
Solution Approach 2:
The tracking cells are designed to mirror the structure and behavior of nominal memory cells, creating accurate copies that emulate signal routing delays. This copying approach enables precise timing tracking without requiring additional complex circuitry that would increase capacitance and degrade performance.
2Measurement precision
If additional routing lines are coupled with memory cells for tracking functionality, then timing tracking is enabled, but power efficiency decreases
Solution Approach 1:
By routing tracking signals through backside metallization layers, the patent reduces the capacitive load on frontside memory cell circuits. This dimensional separation minimizes parasitic effects and reduces the energy required for signal switching and propagation, thereby improving power efficiency while maintaining timing tracking functionality.
3Measurement precision
If tracking cells are integrated with additional metallization layers, then timing tracking functionality is achieved, but device complexity increases
Solution Approach 1:
The backside metallization layers are designed to serve multiple functions: they provide power supply connections, ground connections, and signal routing for tracking cells. This multi-functionality approach consolidates multiple routing needs into a single structural solution, reducing overall device complexity despite the addition of tracking functionality.
Data Source
AI summary
Memory circuits with tracking cells are provided. A memory circuit includes a memory array comprising a plurality of first memory cells. The memory circuit includes a tracking column comprising one or more second memory cells. Each of the second memory cells is coupled to a first metallization layer disposed on a first side of a substrate and a second metallization layer disposed on a second side of the substrate, the second side opposite to the first side. The second metallization layer is configured to receive, from the second memory cells, a level of an internal node of a memory node. The first metallization layer is configured to provide, to the second memory cells, at least one supply voltage.