Variable Resistance Memory Cell Array Position-Dependent Voltage Control
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Solution Overview
Problem
The integration of semiconductor memory devices faces challenges due to variations in the characteristics of Resistive RAM (ReRAM) during manufacturing, particularly in achieving precise dimension and position accuracies of circuit patterns, which affects the reliability and performance of memory cells.
Innovation Solution
A semiconductor memory device configuration that includes a memory cell array with variable resistance elements between word-lines and bit-lines, utilizing voltage adjustment circuits to control voltages applied to the lines based on their position, ensuring consistent resistance changes and operational states, thereby addressing the variability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ReRAM variable resistance elements are used to achieve higher integration, then memory cell array integration is improved, but manufacturing precision deteriorates due to variation in characteristics
Solution Approach 1:
The patent applies local quality by making the conductive layers have different thicknesses at different positions (first, second, and third thicknesses) to locally compensate for manufacturing variations. This allows each region to be optimized for its specific characteristics, addressing the precision issues while maintaining high integration.
Solution Approach 2:
The patent changes the physical parameter of conductive layer thickness to compensate for manufacturing variations. By varying the thickness of different conductive layers, the resistance characteristics are adjusted to achieve uniform memory cell performance despite manufacturing imprecision.
2Ease of manufacture
If conductive layers with varying thicknesses are used, then ease of manufacture is improved, but reliability deteriorates due to inconsistent resistance changes
Solution Approach 1:
The patent systematically varies the thickness parameters of conductive layers to compensate for manufacturing variations. This controlled parameter change ensures that despite ease of manufacture with varying thicknesses, the resistance changes remain consistent across all memory cells.
Solution Approach 2:
The patent implements a feedback mechanism where the resistance characteristics of memory cells are measured and used to adjust the conductive layer thickness in subsequent manufacturing steps, ensuring consistent resistance changes while maintaining manufacturing ease.
3Reliability
If voltage adjustment circuits are added to control voltages based on position, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the voltage control function by providing different thicknesses for different conductive layers, which naturally creates position-dependent voltage distribution. This segmentation approach achieves reliable read/write operations without requiring additional complex voltage adjustment circuits.
Solution Approach 2:
The patent makes the conductive layer structure itself perform the voltage adjustment function through its varied thickness design. The structure self-regulates the voltage distribution to compensate for manufacturing variations, eliminating the need for separate voltage adjustment circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration and reliability of semiconductor memory devices by ensuring uniform resistance changes and correct read/write operations, even with varying conductive layer thicknesses, thereby improving data storage and retrieval accuracy.
Implementation Method 1
a variable resistance element that reversibly changes the resistance
Data Source
AI summary
A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.