Reverse Current Circuit Prevents Read Disturbance
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Solution Overview
Problem
Current semiconductor memory technologies face read disturbance issues during read operations, which can unintentionally change data values due to structure and operating characteristics, and existing write back technologies consume more current and time, potentially harming memory cell lifespan.
Innovation Solution
A semiconductor device with a reverse read control circuit and reverse current generation circuit that selectively generates a reverse current based on the resistance state of the memory cell, preventing read disturbance by activating or deactivating the reverse read control signal and current accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write back technology is used to prevent read disturbance, then read disturbance is prevented, but current consumption increases
Solution Approach 1:
The patent changes the current direction parameter by applying reverse current in the opposite direction to the read current. This parameter change allows prevention of read disturbance without requiring full write circuit operation, thereby reducing current consumption while maintaining reliability
Solution Approach 2:
The patent applies inversion by using reverse current flowing in the opposite direction through the memory cell. Instead of using the conventional write back approach with substantial write circuits, the inverted approach uses reverse current to cancel out the read disturbance effect, achieving prevention with lower current consumption
2Reliability
If write back technology is used to prevent read disturbance, then read disturbance is prevented, but operating time increases
Solution Approach 1:
The patent changes the current direction parameter by applying reverse current in the opposite direction to the read current. This parameter change allows prevention of read disturbance without requiring full write circuit operation, thereby reducing operating time while maintaining reliability
Solution Approach 2:
The patent applies inversion by using reverse current flowing in the opposite direction through the memory cell. Instead of using the conventional write back approach with substantial write circuits, the inverted approach uses reverse current to cancel out the read disturbance effect, achieving prevention with shorter operating time
3Reliability
If write back technology is used to prevent read disturbance, then read disturbance is prevented, but memory cell lifespan deteriorates
Solution Approach 1:
The patent changes the current direction parameter by applying reverse current in the opposite direction to the read current. This parameter change allows prevention of read disturbance without requiring full write circuit operation, thereby reducing stress on memory cells and extending lifespan while maintaining reliability
Solution Approach 2:
The patent applies inversion by using reverse current flowing in the opposite direction through the memory cell. Instead of using the conventional write back approach with substantial write circuits, the inverted approach uses reverse current to cancel out the read disturbance effect, reducing wear on memory cells and improving lifespan
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents read disturbance, reduces current consumption and operating time, and improves memory cell lifespan compared to conventional write back methods, enhancing operational reliability and performance.
Implementation Method 1
Each of the plurality of memory cells may include a variable resistance element having a resistance state varied depending on a direction of the read current
Data Source
AI summary
Disclosed is a semiconductor device, including a memory cell array including a plurality of memory cells, a read circuit suitable for generating read data corresponding to a read current flowing in a first direction through a selected memory cell of the plurality of memory cells, a reverse read control circuit suitable for generating a reverse read control signal corresponding to the read data, and a reverse current generation circuit suitable for generating a reverse current flowing in a second direction through the selected memory cell in response to the reverse read control signal.