Test Circuit with Comparison Control for Semiconductor Memory Yield
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Solution Overview
Problem
Semiconductor device memory cell tests often incorrectly classify memory cells as faulty due to temporary defects caused by environmental factors, leading to decreased test yield when absolute criteria are used, as these cells may be over-screened despite being normally operational.
Innovation Solution
A test circuit with a comparator and comparison control circuit that compares expectation data with read data to generate reference data, allowing for relative test conditions to differentiate between temporary and permanent failures, thereby improving test yield by excluding false fail determinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If absolute test criteria are used to determine memory cell functionality, then screen capacity is improved, but test yield decreases due to over-screening of temporarily abnormal cells
Solution Approach 1:
The patent changes the test parameter from absolute criteria to relative criteria by comparing read data with expectation data. This allows the test to adapt to temporary environmental variations while maintaining detection of permanent defects, thus improving test yield without sacrificing screen capacity
Solution Approach 2:
The patent introduces expectation data as an intermediary reference to mediate between the read data and the fail determination. This intermediary allows for relative comparison that can distinguish between temporary abnormalities and permanent defects, resolving the contradiction between screen capacity and test yield
2Measurement precision
If strict fail determination criteria are applied, then defective memory cells are identified, but normally operational cells are incorrectly classified as faulty
Solution Approach 1:
The patent performs preliminary generation of expectation data before the actual test comparison. This preliminary action establishes a reference baseline that accounts for temporary environmental factors, enabling more accurate distinction between temporary and permanent defects during the test
Solution Approach 2:
The patent implements a feedback mechanism where the comparison between read data and expectation data provides information about temporary versus permanent defects. This feedback allows the test system to adjust its determination, reducing false fails while maintaining defect detection capability
Data Source
AI summary
A test circuit includes a comparator and a comparison control circuit. The comparator is configured to compare a first input signal with a second input signal to generate a comparison result signal. The comparison control circuit is configured to perform at least one of an operation for latching the comparison result signal as reference data and an operation for outputting the comparison result signal as a first output signal. The comparison control circuit is configured to provide expectation data as the first input signal and read data as the second input signal in accordance with the reference data.