Clock Divider Shift Register for DDR Memory Timing
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Solution Overview
Problem
Conventional solutions for generating clock signals for DDR memory devices on DIMM boards are inefficient due to high power consumption, heat generation, and area requirements, particularly in phase locked loops (PLLs) and delay locked loops (DLLs), which fail to precisely meet timing requirements and introduce jitter, making them unsuitable for high-speed applications.
Innovation Solution
An electronic device utilizing a clock divider and shift register to generate phase-shifted clock signals, eliminating the need for PLLs or DLLs, with differential flip-flops and a multiplexer to select optimal clock signals, reducing power consumption and chip area while minimizing jitter and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If phase locked loops (PLLs) or delay locked loops (DLLs) are used to generate clock signals, then timing requirements can be met, but power consumption and chip area increase significantly
Solution Approach 1:
The patent extracts the essential function of clock signal phase shifting from complex PLL/DLL circuits and implements it using a simple shift register composed of flip-flops. This removes the unnecessary complexity while retaining the core timing adjustment capability, thereby reducing power consumption significantly.
Solution Approach 2:
The invention replaces expensive, complex PLL/DLL circuits with inexpensive flip-flop based shift registers. Although flip-flops are simpler components, they achieve the required timing function with much lower power consumption and cost, effectively using 'cheap' components to solve the problem.
2Manufacturing precision
If phase locked loops (PLLs) or delay locked loops (DLLs) are used to generate clock signals, then timing requirements can be met, but chip area consumption increases
Solution Approach 1:
The patent extracts the essential function of clock signal phase shifting from complex PLL/DLL circuits and implements it using a simple shift register composed of flip-flops. This removes the unnecessary complexity while retaining the core timing adjustment capability, thereby reducing chip area significantly.
Solution Approach 2:
The invention replaces expensive, complex PLL/DLL circuits with inexpensive flip-flop based shift registers. Although flip-flops are simpler components, they achieve the required timing function with much lower chip area, effectively using 'cheap' components to solve the problem.
3Power
If conventional clock generation methods are used, then clock signals can be generated, but jitter accumulates and timing accuracy deteriorates
Solution Approach 1:
The patent uses multiple flip-flops to create multiple copies of the clock signal with different phase shifts. Each flip-flop produces an identical copy of the clock signal but delayed by one clock cycle, allowing selection of the optimal phase without accumulating jitter from complex processing circuits.
Data Source
AI summary
A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLK 21, . . . , CLK32) to serve as an output clock signal for transmission of the buffered data to a memory device.