Shared Temperature Control Circuit for DRAM Bank Refresh
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Solution Overview
Problem
Existing semiconductor memory devices, such as DRAMs, face challenges in reducing power consumption and optimizing circuit area due to the need for multiple temperature sensing and control circuits, which complicates precise refresh control and increases power usage.
Innovation Solution
A semiconductor memory device with a shared temperature control circuit that connects multiple temperature sensing circuits to reduce the occupied area on the chip, allowing for separate and selective control of refresh intervals for each memory bank using a time-division multiplexing scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple temperature sensing circuits and control circuits are incorporated for precise refresh control, then measurement precision and reliability are improved, but device complexity and occupied area increase
Solution Approach 1:
The patent combines multiple temperature sensing circuits with a single shared control circuit, merging the control functions that would otherwise be duplicated. This allows precise temperature sensing across multiple memory banks while reducing the total number of control circuits and their associated calibration logic, directly resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The shared control circuit is designed to serve multiple temperature sensing circuits simultaneously, making it a universal component that can handle calibration and control for the entire memory device. This multi-functional approach eliminates the need for separate control circuits for each temperature sensing unit, reducing overall complexity while maintaining precision
2Reliability
If multiple temperature sensing circuits and control circuits are incorporated, then reliability of refresh control is improved, but occupied area increases
Solution Approach 1:
By merging multiple control functions into a single shared control circuit, the patent significantly reduces the total occupied area on the chip. The shared circuit occupies less space than multiple separate control circuits would require, while still providing reliable refresh control through centralized management of all temperature sensing circuits
Solution Approach 2:
The patent transitions from a distributed architecture (multiple control circuits spread across the chip) to a centralized architecture (single shared control circuit). This dimensional reorganization consolidates the control functionality, reducing the spatial footprint and occupied area while maintaining comprehensive coverage for reliable refresh control
3Reliability
If refresh interval is decreased to maintain data retention at higher temperatures, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic refresh interval adjustment based on real-time temperature sensing. The refresh interval is not fixed but adapts to changing temperature conditions, allowing the system to maintain reliable data retention while optimizing power consumption by using shorter intervals only when necessary (at higher temperatures) and longer intervals when temperatures are lower
Solution Approach 2:
The system changes the refresh interval parameter in response to temperature variations. By monitoring temperature through the sensing circuits and adjusting the refresh interval accordingly, the patent achieves reliable data retention across different thermal conditions while minimizing power consumption by avoiding unnecessarily frequent refreshes at lower temperatures
Data Source
AI summary
A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding memory bank. The shared control circuit is connected to the plurality of temperature sensing circuits and a plurality of refresh circuits for refreshing the plurality of memory banks, performs calibration on the plurality of temperature sensing circuits, performs digital processing on signals for separately controlling refresh intervals for the plurality of memory banks, and transmits the processed signals to the plurality of refresh circuits. Therefore, the refresh intervals for individual channels or banks are separately or selectively controlled. Further, since the plurality of temperature sensing circuits are connected to the shared temperature control circuit, the occupied area of the circuits in a chip is reduced or minimized.