Cross-Point Memory Socket Layout for Multi-Deck Array Scaling
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Solution Overview
Problem
Existing memory systems face challenges in efficiently coupling access lines to decoders in cross-point type systems that include more than four decks, leading to complex socket arrangements and increased costs.
Innovation Solution
A cross-point type memory system is designed with novel socket configurations, dividing the memory array into a grid of sub-blocks and arranging sub-blocks according to specific periods, with sockets intersecting access lines at the middle or end, to facilitate efficient coupling of access lines to decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional socket arrangements are used in cross-point memory systems with more than four decks, then the memory system can be constructed, but the socket arrangement becomes complex and costs increase
Solution Approach 1:
The memory array is divided into multiple sub-blocks, each sub-block containing a specific number of memory cells arranged in a grid pattern. This segmentation allows the memory system to scale to more than four decks by organizing memory cells in manageable units that can be systematically connected to decoders through standardized socket arrangements, thereby reducing overall system complexity while maintaining adaptability.
Solution Approach 2:
The patent extends the memory architecture from traditional two-dimensional arrangements to three-dimensional stacking with more than four decks. By adding the vertical dimension and organizing sub-blocks across multiple decks, the system achieves higher memory density and adaptability. The socket arrangements are designed to accommodate this multi-deck structure, connecting access lines to decoders in a systematic manner that reduces complexity despite the increased vertical integration.
2Quantity of substance
If more than four decks are integrated in memory systems, then memory cell density is enhanced, but socket arrangement complexity increases and production costs rise
Solution Approach 1:
By dividing the memory array into multiple sub-blocks across more than four decks, the patent achieves higher memory cell density. Each sub-block is independently organized, allowing for standardized manufacturing processes. This segmentation enables systematic assembly and testing, reducing production complexity despite the increased number of decks, and ultimately lowering per-unit costs through efficient manufacturing scalability.
Solution Approach 2:
The patent changes the architectural parameter from traditional four-deck or fewer configurations to more than four decks. This parameter change increases memory cell density while the accompanying socket arrangement design maintains manufacturing ease by providing a scalable, systematic connection method that can be produced using standardized processes, thereby controlling production costs despite the increased complexity.
3Reliability
If access lines are coupled to decoders in traditional arrangements, then the system functions, but yield impacts commercial viability when scaling to more than four decks
Solution Approach 1:
The memory array is divided into multiple sub-blocks, each with standardized connections to decoders. This segmentation allows for modular testing and assembly, improving yield by enabling individual sub-block validation before full system integration. The systematic socket arrangement reduces complexity by providing repeatable connection patterns across more than four decks, making the system commercially viable through improved manufacturing yield.
Solution Approach 2:
The patent modifies the architectural parameter to support more than four decks with redesigned socket arrangements that maintain reliable connections between access lines and decoders. This parameter change improves yield by establishing robust, scalable connection methods that reduce manufacturing defects and variability, thereby enhancing commercial viability despite the increased system complexity.
Data Source
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AI summary
Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.