Semiconductor Memory Dynamic Amplifier Activation
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Solution Overview
Problem
Conventional semiconductor memory devices are limited in the number of bits that can be simultaneously accessed due to the restricted area where second amplifier circuits (DA/WAs) are placed, leading to increased chip size when trying to enhance data input/output operations.
Innovation Solution
The solution involves activating second amplifier circuits not adjacent to the selected memory mat, using LIO bypass wires to connect them for data amplification, thereby increasing the number of bits that can be read or written without expanding the chip area by compartmentalizing the memory device further.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of DA/WAs is increased to increase the number of MIOs and bits to be simultaneously read out, then the data input/output speed is improved, but the chip area increases
Solution Approach 1:
The patent makes the DA/WA configuration dynamic by selectively activating different numbers of DA/WAs based on the memory access pattern. When a single memory mat is accessed, only 2 DA/WAs are activated; when multiple memory mats are accessed, up to 6 DA/WAs can be activated. This dynamic activation allows the system to achieve high-speed data transfer when needed while minimizing the effective area usage during normal operation.
Solution Approach 2:
The patent makes the DA/WA circuits multi-functional by enabling them to serve different purposes based on activation. The same physical DA/WA circuits can function as active amplification circuits when needed, or be inactivated to reduce effective area. The inactivated DA/WAs still occupy physical space but consume minimal power and can be quickly activated when high-speed access is required, providing universal functionality across different operating conditions.
2Productivity
If the division number of memory cell mats is increased to increase the number of MIOs, then the number of simultaneously accessed bits is improved, but the chip area increases
Solution Approach 1:
The patent implements dynamic control of DA/WA activation based on the number of accessed memory mats. The system can adaptively activate 2, 4, or 6 DA/WAs depending on the access pattern, allowing high bit-width access when multiple mats are accessed without permanently increasing the effective area. This dynamic adaptation resolves the contradiction between simultaneous access capability and area usage.
Solution Approach 2:
The patent segments the DA/WA activation into different groups based on which memory mats are accessed. When memory mats MT1-MT6 are accessed, different combinations of DA/WAs (1,3,5 or 2,4,6) are activated. This segmentation allows the system to achieve high simultaneous bit access by distributing the data across multiple access paths while using the same physical DA/WA resources, avoiding the need to increase chip area.
Data Source
AI summary
A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input output lines coupled to the second memory mat via a second amplifier circuit; a third amplifier circuit coupled between the first local input output line and a first main input output line; a fourth amplifier circuit coupled between the third local input output line and a second main input output line different from the first main input output line; and a first switch coupled between the second and third local input output lines and connecting the second local input output line to the fourth amplifier circuit when the first memory mat is activated and the second memory mat is not activated.