Segmented Memory Bus Architecture for Variable Read/Write Bandwidth
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Solution Overview
Problem
The unbalanced development between processor and memory performance leads to a storage bottleneck, restricting high-performance computing, and network devices face challenges in meeting varying memory bandwidth requirements for different data types.
Innovation Solution
A memory architecture with multiple channels, each corresponding to distinct read/write bus groups, allowing adaptive use based on bandwidth requirements, and a network device incorporating this memory to manage different read/write operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory bandwidth is increased by increasing storage transmission rate (e.g., DDR storage), then memory bandwidth is improved, but it becomes difficult to meet varying read/write bandwidth requirements for different data types in network devices
Solution Approach 1:
The memory bus is segmented into multiple independent bus groups, where each bus group can be independently configured and controlled. This segmentation allows different bus groups to serve different data types with appropriate read/write bandwidth allocations, resolving the contradiction between high memory bandwidth and adaptability to varying requirements.
Solution Approach 2:
The memory bus groups are designed to be dynamically configurable, allowing the system to adapt bus allocation based on real-time data access patterns. This dynamic capability enables the memory subsystem to switch between different read/write bandwidth configurations, simultaneously achieving high performance and flexibility.
2Productivity
If a single memory bus configuration is used, then device complexity is reduced, but the ability to meet different memory bandwidth requirements for service packets and service entries is compromised
Solution Approach 1:
Each memory bus group is designed with multi-functionality, capable of serving both read and write operations with configurable bandwidth allocation. This universal design allows the same bus structure to adapt to different data types (service packets, service entries) without requiring entirely separate bus configurations, thus managing complexity while meeting diverse bandwidth requirements.
Data Source
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AI summary
A memory, a network device, and a data access method are provided, and related to the field of memory technologies, to meet requirements of a same storage device for different memory bandwidths. The memory includes at least one channel. The at least one channel includes a first channel. The first channel corresponds to a first read bus group and a first read/write bus group. The first read bus group is configured to read data of the first channel. The first read/write bus group is configured to read data of the first channel or write data into the first channel.