Semiconductor Memory Data Input Circuit for Multi-Mode Support
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Solution Overview
Problem
The complexity and increased circuit area in semiconductor memory devices due to the need for numerous data input circuits to support various data bit modes, such as X16, X8, and X4, result in a cumbersome layout with excessive lines and switches required for data transfer.
Innovation Solution
A semiconductor memory device with a simplified data input circuit design that includes input buffers, selectors, and alignment circuits to efficiently align and transfer data across global lines based on the data input mode, reducing the number of lines and switches needed by routing data directly to the appropriate storage locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 16 data input circuits are provided to support X16, X8, and X4 modes, then the semiconductor memory device can operate in all data input modes, but the circuit area increases considerably and the circuit becomes too complicated
Solution Approach 1:
The patent implements a universal data input circuit design where a single circuit structure can handle multiple data input modes (X16, X8, X4) by selectively activating different input buffers and data selectors. The data input circuit includes multiple input buffers that can be selectively enabled based on the operating mode, allowing one circuit to perform multiple functions without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The data input circuit is segmented into multiple independent input buffers (first input buffer, second input buffer, etc.), each handling specific data bits. The data selector circuit then combines outputs from these segmented buffers based on the operating mode. This segmentation allows the circuit to process data in different configurations (4-bit, 8-bit, 16-bit) by selectively activating appropriate segments.
2Adaptability or versatility
If 16 data input circuits are provided to support all data input modes, then the semiconductor memory device can receive data of various numbers of bits, but the circuit area increases considerably
Solution Approach 1:
The patent implements a universal data input circuit design where a single circuit structure can handle multiple data input modes (X16, X8, X4) by selectively activating different input buffers and data selectors. The data input circuit includes multiple input buffers that can be selectively enabled based on the operating mode, allowing one circuit to perform multiple functions without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The patent merges the functionality of multiple data input circuits into a single integrated data input circuit structure. By combining multiple input buffers, data selectors, and alignment circuits into one unified circuit, the patent reduces the total circuit area while maintaining the capability to support X16, X8, and X4 modes through selective activation of circuit components.
3Ease of operation
If data transfer lines are added to transfer data in X4 and X8 modes, then data can be conveyed to designated areas, but lots of lines are required which makes the layout complicated
Solution Approach 1:
The data transfer lines are designed to be universal, serving multiple purposes across different operating modes. The same data transfer lines used in X16 mode also serve X8 and X4 modes through the selective activation of input buffers and data selectors. This eliminates the need for separate dedicated data transfer lines for each mode, reducing the total number of lines required.
Solution Approach 2:
The data alignment circuit performs preliminary alignment of data from multiple input buffers before the data is transferred to the data storage area. By pre-aligning the data in the correct positions based on the operating mode, the patent simplifies the subsequent data transfer process and reduces the complexity of the data transfer line routing.
Data Source
AI summary
A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector.