Master-Slave DRAM Power Gating for Category-Based Energy Reduction
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Solution Overview
Problem
Existing DRAM devices consume excessive power due to the use of both first and second category DRAM chips, leading to increased power consumption in certain product categories.
Innovation Solution
Incorporating a slave DRAM chip with a slave power circuit that stops generating voltages in response to a control signal when a first category DRAM chip is used, and a master DRAM chip that controls the slave chip's operation, thereby reducing power consumption by selectively activating or deactivating voltage generation based on the category of DRAM chip employed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both first category DRAM chip and second category DRAM chip are used in the DRAM device, then the functionality and product category versatility is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic power management by making the voltage generation capability of the slave power circuit controllable through a control signal. The slave power circuit can dynamically switch between generating slave voltages and stopping voltage generation based on the control signal value, allowing the system to adapt its power consumption to the actual product category and operational requirements
Solution Approach 2:
The patent changes the operational state parameter of the slave power circuit from a fixed state to a variable state. By modifying the control signal (first value vs. second value), the slave power circuit transitions between different operational modes: generating slave voltages or stopping voltage generation, thereby adjusting power consumption parameters according to the first or second product category
2Use of energy by moving object
If the slave power circuit stops generating slave voltages, then the power consumption is reduced, but the functionality for second category DRAM device is lost
Solution Approach 1:
The slave power circuit is designed with dynamic controllability, where the generation of slave voltages can be switched on or off based on the control signal. This dynamic capability allows the system to adapt between first product category (power saving mode with voltage generation stopped) and second product category (full functionality mode with voltage generation active)
Solution Approach 2:
The slave power circuit is designed to serve multiple product categories through a single unified structure. By incorporating the control signal input mechanism, the same slave power circuit can fulfill different functional requirements: supporting both first category DRAM devices (where power consumption is reduced) and second category DRAM devices (where full functionality is required)
Data Source
AI summary
A dynamic random-access memory (DRAM) device is provided. The DRAM device includes a slave DRAM chip and a master DRAM chip. The slave DRAM chip includes a slave control circuit and a slave power circuit. The slave control circuit generates a slave control signal according to a slave category signal and a setting signal. The slave power circuit stops generating at least one of slave voltages in response to a first value of the slave control signal and generates the slave voltages in response to a second value of the slave control signal. The master DRAM chip includes a master control circuit. The master control circuit generates a master control signal according to a master category signal and the setting signal, and controls the master DRAM chip to generate master voltages according to the master control signal. The slave category signal is different from the master category signal.