SRAM Chip FinFET Tracking Cells Cross-Talk
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, issues such as cross-talk and wiring resistance affect their performance, particularly in static random access memory (SRAM) devices, where existing solutions fail to adequately address these challenges.
Innovation Solution
The implementation of a memory cell structure that incorporates three-dimensional gate structures, such as fin field-effect-transistors (FinFETs), with a combination of single-fin and multiple-fin transistors, and the use of tracking bit lines and write assist circuits to improve memory cell performance without requiring read assist circuitry for all cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistor structures are used in SRAM devices, then manufacturing is simpler and cost is lower, but cross-talk and wiring resistance adversely affect performance as ICs become smaller and more complex
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to three-dimensional FinFET structures. This dimensional change enables better gate control over the channel, reducing the harmful effects of cross-talk and wiring resistance while maintaining scalability for high-density integration.
Solution Approach 2:
The patent changes the physical and geometric parameters of the transistor structure by introducing vertical fins with controlled widths and heights. This parameter change improves the gate-to-channel control ratio, thereby mitigating cross-talk and wiring resistance effects without requiring read assist circuitry.
2Reliability
If three-dimensional FinFET structures are implemented to reduce cross-talk and wiring resistance, then SRAM performance improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the transistor channel into multiple vertical fins, each independently controlled by the gate. This segmentation allows better electrostatic control and reduced cross-talk while maintaining a scalable structure that can be manufactured using extended CMOS processes.
Solution Approach 2:
The FinFET structure serves multiple functions simultaneously: it provides better gate control, reduces cross-talk, enables higher density, and maintains compatibility with standard CMOS manufacturing processes, thereby managing complexity while achieving performance improvements.
3Reliability
If read assist circuitry is added to all memory cells to improve performance, then reliability improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the read assist circuitry from being a universal requirement for all memory cells and retains it only where specifically needed. The improved FinFET-based memory cell structure achieves sufficient performance without read assist circuitry in most cases, reducing overall device complexity and manufacturing cost.
Solution Approach 2:
The memory cell structure itself is designed to provide the necessary performance characteristics through its FinFET architecture, eliminating the need for external read assist circuitry to compensate for structural deficiencies. The structure serves its own performance requirements through optimized gate control and reduced cross-talk.
Data Source
AI summary
A static random access memory (SRAM) chip includes a first and second conductor, a set of SRAM cells and a set of first and second tracking cells. The first conductor extends in a first direction, is coupled to a first supply voltage, and on a first metal layer. The second conductor extends in a second direction, is coupled to a second supply voltage, and on a second metal layer. A first cell of the set of first tracking cells includes a first tracking bit line conductor, first and second CMOS, and a first and second pass gate device. A first cell of the set of second tracking cells includes a third pass gate device, a third PU device, and a third PD device having a source configured to be electrically floating. A gate of the first PD device or the first PU device is electrically coupled to the first conductor.