Negative Word-Line Bias Control for DRAM Leakage Refresh
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Solution Overview
Problem
Memory devices, particularly DRAM, suffer from data corruption due to leakage currents that vary with environmental and manufacturing factors, necessitating frequent refresh operations, which disrupt normal read and write operations.
Innovation Solution
A feedback circuit is implemented to control leakage current by applying a negative bias voltage to word lines, using a reference cell array and comparator to maintain the leakage current at a preset value, thereby stabilizing refresh frequency and improving read/write efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to maintain data integrity in DRAM, then data reliability is improved, but read and write operations are disrupted
Solution Approach 1:
The patent implements a feedback circuit that continuously monitors leakage current and dynamically adjusts the refresh frequency accordingly. The circuit compares the measured leakage current against reference values and automatically modifies the refresh operation timing, allowing the system to maintain data integrity while reducing unnecessary refresh operations that disrupt read/write operations.
Solution Approach 2:
The refresh frequency is made dynamic rather than fixed. The system continuously adapts the refresh rate based on real-time leakage current measurements, environmental conditions, and workload patterns. This dynamic adjustment allows the memory controller to optimize between data reliability and operational efficiency by refreshing only when necessary.
2Reliability
If leakage current is reduced through circuit modifications, then refresh frequency requirements are reduced, but device complexity increases
Solution Approach 1:
The memory system performs self-diagnosis and self-adjustment by incorporating leakage current sensing and feedback control within the memory controller itself. The system automatically monitors its own leakage characteristics and adjusts refresh operations without requiring external intervention or complex external control circuits, thereby managing complexity while achieving reliable leakage control.
Solution Approach 2:
The leakage current sensing function, reference voltage generation, and refresh control logic are merged into an integrated feedback circuit within the memory controller. By combining these functions into a unified control mechanism rather than separate systems, the patent achieves effective leakage control while minimizing the increase in overall device complexity.
3Reliability
If negative bias voltage is applied to word lines to control leakage, then leakage current is reduced, but additional control circuitry is required
Solution Approach 1:
The negative bias voltage generator is designed to serve multiple functions: it provides the negative bias voltage for leakage suppression during standby modes, generates reference voltages for the feedback comparison circuit, and can be controlled through the existing refresh control logic. By making the voltage generator multi-functional, the patent achieves effective leakage control without requiring entirely separate control circuitry.
Solution Approach 2:
The feedback control circuit acts as an intermediary that translates leakage current measurements into appropriate negative bias voltage adjustments. Rather than directly controlling individual word lines, the system uses the feedback mechanism to modulate the negative bias voltage level, which then uniformly affects leakage suppression across multiple word lines, simplifying the control architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution stabilizes refresh frequency and enhances read/write operations by limiting leakage current, eliminating the need for sensors and ensuring consistent device performance across varying conditions.
Implementation Method 1
a negative voltage generator operative to generate a negative bias voltage in response to the enable signal, wherein the negative bias voltage is applied to a plurality of word lines of the memory device
Data Source
AI summary
Limiting a leakage current of a memory device is provided. A sensing current that is a representative of a leakage current of a memory cell array of a memory device is generated. A reference current having a preset value is generated. The sensing current is compared with the reference current. An enable signal is generated based on the comparison. A bias voltage applied to a plurality of word lines of the memory cell array is adjusted based on the enable signal.