SRAM Ground Line Charge Sharing for Low-Voltage Write Assist
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Solution Overview
Problem
Static random access memory (SRAM) devices face challenges in reducing power consumption while maintaining writability, especially at low power supply voltages, due to increased process variation and threshold voltage distribution, leading to potential write failures and increased power consumption in existing write assist methods.
Innovation Solution
A method for operating memory cells involves a standby state with precharge voltage and ground connection, followed by charge sharing between bitlines and the ground line, and then applying a voltage pulse to the wordline for writing, which improves writability and reduces power consumption by optimizing voltage swings and charge sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is reduced to lower power consumption, then power consumption is reduced, but writability of memory cells deteriorates due to insufficient voltage to overcome transistor threshold voltage
Solution Approach 1:
The ground line is precharged to a voltage level close to the power supply voltage before the write operation begins. This preliminary action creates a reduced voltage swing requirement for the bitlines, allowing the memory cell to be written successfully even at low power supply voltages where the available voltage margin is limited.
Solution Approach 2:
The ground line serves as an intermediary element that is coupled to both the bitlines and the power supply voltage source during the write operation. By raising the ground line voltage, it mediates the voltage distribution in the memory cell, effectively reducing the threshold voltage requirement for the access transistors and enabling successful writes at low supply voltages.
2Reliability
If existing write assist methods are used to improve writability, then writability is improved, but power consumption increases or chip area increases
Solution Approach 1:
The ground line is given a dual function: it serves as the conventional ground reference during normal operation and as a voltage storage line that can be precharged to assist writes during low-voltage operation. This multi-functionality eliminates the need for separate write assist circuitry, avoiding additional power consumption and chip area overhead.
Solution Approach 2:
The invention changes the voltage parameter of the ground line dynamically - it is precharged to a high voltage level (close to VDD) before write operations at low supply voltage, then discharged back to ground level afterward. This parameter change enables improved writability during the critical write window without permanently altering the ground reference or requiring continuous power consumption.
3Productivity
If technology scaling is applied to reduce critical dimensions, then device integration is improved, but process variation increases leading to broader threshold voltage distribution and reduced writability
Solution Approach 1:
The ground line is precharged to a voltage level that provides a margin of safety against process variation. By establishing this voltage cushion before the write operation, the invention compensates for the broader threshold voltage distribution caused by scaling-induced process variation, ensuring that even memory cells with higher-than-average threshold voltages can be written successfully.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the writability of memory cells at low power supply voltages, reduces power consumption, and minimizes the likelihood of write failures, while maintaining efficient operation in low-speed, low-power applications.
Implementation Method 1
the bitline is electrically connected to the ground line for charge sharing between the bitline and the ground line
Data Source
AI summary
Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell.